Really two questions:
1. How is it that is works with either mode without (non existent) re-configuration?
It looks like all the data will be shifted by 1 bit if you use the wrong mode.
But it seems to work fine.
2. Why does the official Analog Devices USBi use the wrong mode!
You have discovered that the ADAU1452 datasheet declares the SPI slave interface as Mode 3, and yet the USBi uses SPI Mode 0. Both statements are correct. The ADAU1452 ignores the leading and trailing falling edges of SCLK, so both Mode 0 and Mode 3 masters will work with the ADAU1452 slave port.
Microcontroller interfaces should work fine over both Mode 0 and Mode 3. If it's a simple library initialization call to switch between them, you might as well use Mode 3, since the datasheet defines the interface that way.
The following image from https://www.corelis.com/education/tutorials/spi-tutorial/ may help clear things up.
The difference between SPI Mode 0 (CPOL=0, CPHA=0) and SPI Mode 3 (CPOL=1, CPHA=1) is a half-cycle shift in SCLK. The DSP does not care about the first SCLK falling edge shown in Mode 3, or about the final SCLK falling edge in Mode 0. Since the protocols are otherwise identical data is transferred properly in both directions under both setups.
SPI modes 1 and 2, however, will NOT work with the ADAU1452 slave port because outgoing data is read on the falling edge of SCLK instead of the rising edge.
This scope capture shows an SPI data packet being transferred from the USBi to the DSP. You can see that when /SS is pulled low, SCLK is low, and the first rising edge of SCLK corresponds to the first valid data bit. This confirms your finding that the USBi must be using SPI Mode 0.
By the way, I didn’t notice that the USBi uses SPI Mode 0 until now. Good find!