I'm seeing some unexpected behavior with the voltage-controlled fractional delay block in SigmaStudio. The processor I'm using is the ADAU1466 with a sample rate of 48kHz. The maximum delay in the block is 36000 samples (750ms at 48kHz).
When setting the input voltage to 0V using a DC source, I'm seeing a delay of roughly 615ms (should be 0ms). When setting the input voltage to 0.0625V (1/16V step size), I'm seeing a delay of roughly 662ms (should be 46.875ms) . Larger step sizes produce the expected delay. For example, 0.125V input produces 93.75ms delay, 0.250V input produces 187.5ms delay and so forth.
Can anyone else confirm this?
I created a simple project that mimics yours but gets around the assembler error with the built-in counter. It also shows evidence of the problem I'm claiming. Note that the delay value is set to 0.0625 and produces an actual delay of 31778 samples (it should be 2250). I tested a delay value of 0.125 and got the expected result. I'm running SigmaStudio version 4.5 Build 0, Rev 1779.
Attached is the project file.Delay_Test3.zip
I confirmed that cascading two delays, each with 1/2 the max delay seems to fix the problem. The 2nd delay shows an incorrect value for the max delay (0ms) but appears to work correctly.
Great, thank you for confirming this. I filed a bug report for these compiler issues.
Ok. Thanks for coming up with a work around.