I'm seeing some unexpected behavior with the voltage-controlled fractional delay block in SigmaStudio. The processor I'm using is the ADAU1466 with a sample rate of 48kHz. The maximum delay in the block is 36000 samples (750ms at 48kHz).
When setting the input voltage to 0V using a DC source, I'm seeing a delay of roughly 615ms (should be 0ms). When setting the input voltage to 0.0625V (1/16V step size), I'm seeing a delay of roughly 662ms (should be 46.875ms) . Larger step sizes produce the expected delay. For example, 0.125V input produces 93.75ms delay, 0.250V input produces 187.5ms delay and so forth.
Can anyone else confirm this?
You are correct. There is a bug in this block and it will be reported to our programming team as soon as I finish typing this.
I’ve found that my project works properly when the delay is set…
I created a small project to test this out. It works by counting up in steps of 1 (in 32.0) and subtracting the delayed value from the original value. I input various values to the delay (including 0, 1/16, 1/4, 1/2, and 1) and each value gave me the expected result.
Can you tell me more about your setup? How are you evaluating the delay block's functionality?
Thanks for your reply. My evaluation was done by measuring the delay between the direct and delayed paths using audio recording software. The project for the test is shown below.
Here's another version that generates a pulsed CW tone using a 1kHz oscillator gated with a 1Hz pulse (1% duty cycle). The audio capture (Reaper software) shows a measured delay of 337ms, not the expected value of 46.875ms.
I attempted to reproduce your test but see an error upon assembling. Any ideas as to the cause?
I’ve found that my project works properly when the delay is set to 32000, but I get an assembler error when the ‘Max Samples’ parameter is set to 36000. As for your original project with the incorrect delays, I tried recreating it but got the same compiler error. Can you attach your project file? What version of SigmaStudio are you using?
In the meantime, I tried cascading two delay blocks as shown below and this seems to work ok. Can you try that in your setup?