Using the Watchdog Counter in the ADAU1452 or the ADAU1467 family of processors.

First let me say that many customers use a GPIO with a counter to create a heartbeat that can be monitored by an external controller. This is certainly one way to do this.

The Watchdog Counter function is not to be confused with the PLL Watchdog. That is a different feature and I will not cover that here.

At this point in time the Watchdog counter will not be automatically reset by the framework code in SigmaStudio. So this must be done in the SigmaStudio Schematic and it is easy to do.

The Watchdog does not have an enable/disable register. There are only two control registers, the Prescaler (0xF444) and the MAXCOUNT (0xF443) registers.

Then there is the Watchdog Panic Code Mask and the actual Watchdog Panic Code flag registers. There are no other registers associated with the Watchdog counter.

If the program is loaded from a DSP reset, AND the MAXCOUNT = 0. The Watchdog counter feature will be disabled.

To enable the Watchdog counter, you do one of these two things:

1. Have the MAXCOUNT register have a non-zero value when the DSP is programmed.
2. Write any value, including zero, to the MAXCOUNT during operation of the DSP and the Watchdog will be enabled.

Once enabled it functions in this way:

The prescale counter will increment every CORE clock cycle and once it reaches the prescale setting of clock cycles it will decrement the Watchdog counter. So if the Prescaler is set to 64, then it will decrement the Watchdog counter every 64 CORE clock cycles.

The Watchdog will continue to be decremented and if it reaches zero, it will set the Watchdog Panic Code Flag. It will continue to set this flag every time it is attempted to be decremented once it has reached zero. In other words, it will not wrap around to 0xFFFFF and start counting over. Once it trips it will stay at zero until it is reset.

So how is the counter reset?

Writing to MAXCOUNT register will set an internal flag that will cause the Watchdog counter to be reset with the value in MAXCOUNT register. So this is the update mechanism. It is assumed that the MAXVALUE being used will not change but that does not matter. The act of writing to this register will trigger the update of the counter during the next core clock cycle.

So the SigmaStudio program I attached will update the Watchdog Max Count  register during every sample frame thereby updating the Watchdog and preventing it from reaching zero. Should the program stop running then it will reach zero and trip the panic code flag. Note, that if the Start Pulse is externally generated, it is possible that if that clock source went away for a period of time the Watchdog would trigger since the code that updates the counter will not be running but the core clock is still running.

In my program I have a switch that allowed me to trigger the error. So here are the calculations:

I have the prescaler set to 64. Core clock is 294.912 MHz.

So 294,912,000 / 64 = 4,608,000. This is the number of times the Watchdog counter will be decremented in a second.

I am running at 48kHz sampling rate so this means that the counter will be decremented 96 times per sample period.

So the MAXCOUNT that is greater than 96 should not trigger the panic code. I used the maximum number of 8,192 just because that is what I was using earlier. If the start pulse is externally generated then I would have at least a small margin so that the jitter/drift of the sample rate would not cause a trigger. So a number of around 500 would mean that the program would have to hang for over five sample periods to trigger the panic code.

In the example program I have a switch to select a “1” as the MAXCOUNT value which will set off the panic code for testing purposes.

Now this brings up the Panic Code system which is another discussion. This can be polled by a controller or it can be tied to a GPIO pin which can be tied to an interrupt driven GPIO pin on the controller to automate this without polling. 

Dave T

ADAU1452 Basic Stereo Input-Vol-Meter-Mute-with Watchdog reset.zip