Kindly let us know whether SPDIF output can be directly routed to DSP without using ASRC or Is it possible to bypass the ASRC with using register setting in 1452.
Our requirement is that input data from SPDIF out has be bit matched for DSP processing with original input used for pumping.
I do not understand what "pumping" is for the context you used the term? However, I do not need to know to answer your question.
The part is capable of directly feeding the SPDIF data to the core but we removed the functionality in SigmaStudio shortly after we released the part. The reason why is that it is not a stable way to run the part. The Start Pulse has to be set to the SPDIF input to prevent lost samples and repeated samples. The problem with that is when the SPDIF looses lock the part stops dead in its tracks without a start pulse. There is nothing you can do in the DSP code to capture that and switch over to another clock source because the core is not running the program. The outputs all stop as well and even if you use an ASRC on the output serial data the source of the data will stop and you will get DC out of the ASRC.
There are very few applications where this behavior is tolerable so we removed the cell that allows you to grab the data directly.
So is the source of other data in your system synchronous to the SPDIF data? In that case you could set the start pulse to this other clock source and grab the data from the SPDIF. This would have to be done in custom code or a custom DLL to give you access to that data. Contact me directly using my Analog email address.
Thanks for feedback.
>>So is the source of other data in your system synchronous to the SPDIF data?
Currently, we are using SPDIF source alone to the system, no other additional sources are used. Kindly let me know, the procedure for creating custom code to access SPDIF data directly.
Sorry, We don't have your email address for contact directly. Kindly share to communicate further via email
>>what "pumping" is for the context you used the term?
"Pumping" , We mean that an input data to DSP from Optical SPDIF device.
I will send you an email once I get more info. I did talk to the designer and he insisted that it does not stop the clocks when the SPDIF receiver PLL loses lock. It just goes back to its natural rate around 48kHz. I need to investigate further and then update my previous post that now looks like was in error. In the next few days I should be able to get to this.
Thanks for reply. Kindly let us know your feedback further if you have.
Thanks & Regards,
Please let us know your feedback for above query.
Through custom DLL, Is it possible to route the SPDIF output to SigmaDSP without ASRC?