we want to use a existing ADAU1467 design with 8kHz sample rate. Therefore 48kHz input shall be routed via ASRC to the core DSP. There computet with 8kHz due to Performance limitations (Long FIR filters) Output shall be also via an ASRC and be resampled to 48kHz again.
I tried different Settings but somewhere there seems to be a mistake. Could you please indicate all necessary changes? Design ot master Clock Crystal is based on reference design.
As far as I assume I Need changes in Clock Settings; Core FS; SDATA in/out.
Are you using your own hardware or one of our evaluation boards?
If it is your hardware it would be good to have some more details. If it is an evaluation board then which one and which revision and how are you connecting to it?
Then please zip your project at attach it to a post. There are far too many things that can be set wrong and it will go much faster if I can click through the register settings and see your signal flow.