3 ADAU1761. sharing 12.288mhz clock. one of them runs at half frequency. An oscillator set to output 500hz outputs 250 hz.. I discovered this problem after i added a test tone to my device.
using 256*48000 for input clock and PLL enabled
So this tells me that all of my filter s were running at half also (or double?) . I looked at the codec and digital settings for all 3 chips, they look the same to me. the other 2 chips putput correct frequency when I add an oscillator in sigma studio. when i build a new bare bones test project for the 3 chips, they all run at correct frequency. It would be a big problem to have to rewrite this from scratch to fix the problem, as front end software is tied to the addressing. Any hints please on what to look for to fix the half frequency problem would be much appreciated.