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ADAU1462-150 PLL and other settings

Hi,

I was starting implementation for the ADAU1462-150 and came accross some points that are unclear for me.

1) The datasheet shows in Table 20 on page 29 the predivider and feedback divider settings.
The table states for a 12.288MHz input a setting of 4 and 96 which would result in 294.912MHz, in the same line there is a value of 147.456MHz for "slow grade" versions.
Is there an additional divider that is automatically set for the 150MHz version?
If not, would the correct setting be 4 and 48 for 147.456MHz system clock? Then 1/3 for the clock generator instead of 1/6 for 48kHz samplerate?

2) What is the purpose of the MULTIPURPOSE1 settings in the Sigma Studio?
I can see writes to address 0xF5D0 etc. but there is no description in the datasheet for this address range or the MODE1 settings.

3) What is the idle state in Table 3 POWER supply and how can I set that state?
I think it's not hibernate as the power consumption is still very high here.

4) Under CORE_CONTROL there is a button START CORE which writes to the register 0xF402 according to the capture window.
But there is no change on the status of the core (signal still running, power consumption no change).
What does this setting?

Also there are still some errors in the datasheet I think like:
- Table 21 shows wrong instruction numbers for samplerates below 48kHz (10 times the correct value)
- Page 89 RANDOM ACCESS MEMORY textual description is wrong (old values from ADAU145x?), tables are ok

Thanks in advance for any answer!

Regards
Christian

Top Replies

  • Hello Christian,

    1) The datasheet shows in Table 20 on page 29 the predivider and feedback divider settings.
    The table states for a 12.288MHz input a setting of 4 and 96 which would result in 294.912MHz, in the same line there is a value of 147.456MHz for "slow grade" versions.
    Is there an additional divider that is automatically set for the 150MHz version?
    If not, would the correct setting be 4 and 48 for 147.456MHz system clock? Then 1/3 for the clock generator instead of 1/6 for 48kHz samplerate?

    The PLL is setup to operate in a fairly narrow range. The PLL for all variants will be in the region of 294.912MHz. Then there is a divider on the PLL output for the variants that operate at ~150MHz. The internal logic takes care of all the proper scaling of all the sub-systems that rely on the system clock. So for instance, the clock generators will divide the system clock by 1024. When the divider is active the pre-divider for the clock generators will be 512. So this difference in the system clock is fully transparent to the user. So much so that I recently had difficulty verifying that the system clock rate was correct in the lab when I needed to do that.

    So for the parts that run at the slower rate you will still setup the PLL for the faster rate, the rest will all be handled automatically.

    What is the purpose of the MULTIPURPOSE1 settings in the Sigma Studio?
    I can see writes to address 0xF5D0 etc. but there is no description in the datasheet for this address range or the MODE1 settings.

    I am not certain where you are seeing these writes to 0xF5D0?

    If you are seeing this on the compiler outputs then SigmaStudio may be writing to these addresses when it does not need to. This address 0xF5D0 is for multipurpose pins that do not exist on the 72 pin parts. They exist on the 88 pin parts only. You will find these in the ADAU1467 datasheet. What may have happened is that the programmers simply copied the SigmaStudio DLL for the 1467 and then made some changes for the 72 pin part. They are almost identical. This detail may have been missed. So this is my first guess before I read your reply.

    What is the idle state in Table 3 POWER supply and how can I set that state?
    I think it's not hibernate as the power consumption is still very high here.

    The Idle state is where the core is not running. You used the word "hibernate", have you set the part into the hibernate mode and then measured the power draw? In hibernate the core is not running the program but it is still active. What this does is simply mask all the interrupts. So the core is executing NOPs. Going into hibernate is the first step in stopping the core. You trigger the hibernate command, then you must wait for the current frame to complete. If you are doing block processing then you must wait for enough frames for the rest of a block to complete. Then at that point it is safe to issue the Stop Core command. This should lower your power consumption.

    Then when you are ready to wakeup you issue the start core command. Then you take the core out of hibernate and you are then running the program again. It is a good idea to be muted during all this.

    I suggest you download the newest version of the ADAU1452 datasheet. I recently did a significant update to the datasheet to correct some errors and misleading information in the original datasheet. This section is one of the sections that I worked on a lot. Some of this is mentioned in the Programming the SigmaDSP Core section and most of it is detailed in the actual register details sections for these registers. Eventually the Sigma350 datasheets (the ADAU1462/63/66/67) will be updated with this information. The basic core of these parts are exactly the same. The changes were in memory and peripherals.

    Under CORE_CONTROL there is a button START CORE which writes to the register 0xF402 according to the capture window.
    But there is no change on the status of the core (signal still running, power consumption no change).
    What does this setting?

    I sort of answered this above. Also, if you read the 1452 datasheet you will see that the start core ONLY starts the core. It cannot stop it. This is an edge triggered register. These are the things I detailed in the newest version. The short quick answer is: You have to hibernate, wait for processing to finish, then Stop the core.Then Start core is used to restart the core.

    Also there are still some errors in the datasheet I think like:
    - Table 21 shows wrong instruction numbers for samplerates below 48kHz (10 times the correct value)
    - Page 89 RANDOM ACCESS MEMORY textual description is wrong (old values from ADAU145x?), tables are ok

    yes, Table 21 had some errors in it. This is one of the things I fixed. Some of the numbers had an extra "0" on the end instead of a superscript "1". I fixed it in the 1452 datasheet and it is exactly the same for the Sigma350 parts.

    Page 89: I agree that the tables look correct. It does look like the text has some issues.I would have to ask the lead Apps guy for that part. I handle the Sigma300 and he hands the Sigma350. Basically, the 1462 is exactly the same as the 1452 for data memory and most of its features. It is meant to be a drop-in replacement to take advantage of a few things we changed. However, there is more program memory. The 1466 doubles the data memory and triples the program memory verses the 1452. So you are correct in that this section could be better written.

    Dave T

  • Hi Dave,

    thank you for your answers, that mostly covers all my points.

    I am not certain where you are seeing these writes to 0xF5D0?

    I was looking to the capture window but as you explained doesn't matter for the ADAU1462.

    I suggest you download the newest version of the ADAU1452 datasheet

    Relating to the power consumption questions and idle/hibernate I will have a look to the ADAU1452 datasheet.

    Regards

    Christian