ADAU1467 Please let me know the correct timing in the system initialization sequence.

Hi,

I have a question about ADAU1467 system initialization sequence.

I'd like to know the timing of the following two events in designing the system.

1. Time to start toggle from hardware reset release.

2. Time when SPI communication is possible after toggle is done.

If there are no exact time, please tell me the  event trigger.

Thanks and Regards,

Parents
  • 0
    •  Analog Employees 
    on Jan 23, 2019 6:20 PM over 2 years ago

    Hello Takumi,

    Figure 13 in the datasheet shows what is involved to get the part to where the control port is active. There is a variable of when the power supplies are stable. So I cannot give a time for when the supply is stable.

    So assuming enough time for the supplies to come up and be stable, then once the reset pin is raised, there are initialization instructions that require 8 cycles of the clock coming into the XTALIN/MCLK pin. Once those instructions are complete, then the control port is active.

    Then at that point you need to toggle the Slave Select pin to place the part into SPI mode. After the toggles the port is active, you only need to wait the minimum time between toggles of the Slave Select pin. Table 13 has that number, the tSSPWH, 10 ns is the required space between when the slave select goes high and when it can go low for the next message. In this case it would be the first message.

    Now, it is important to note, that the speed of the SPI communication, the SPI Clock, must not be greater than the frequency of the incoming clock on the XTALIN/MCLK pin until the PLL locks. Once the PLL locks then the clock speed can be as high as 20MHz.

    Often this is not an issue since most designs use a SPI speed of 10MHz and the incoming crystal/clock is 12.288MHz then the speed can be the same before and after the PLL locks. So if the plans are to use a SPI clock greater than the master clock input pin then you must use a slower speed when configuring and polling the PLL lock bit. Once locked, then the speed can be up to the max specification.

    Thanks,

    Dave T

  • Hi Dave,

    Thanks for your detailed information.

    There are two additional questions.
    Does these regulations exist?

    Please refer to Figure 13.

    1.The time from when the master clock is supplied until the reset pin becomes valid.

       Minimum time or number of cycles that must to be wait.

    2.Time from the reset pin being driven high until the internal reset is completed.

    Thanks and Regards,

  • 0
    •  Analog Employees 
    on Jan 29, 2019 5:36 PM over 2 years ago in reply to takumi3952

    Hello Takumi3952,

    1) The reset pin is valid as long as the power supplies are up and stable and the internal level shifters are active. The reset pin circuit does not require the master clock but the part will do nothing with no master clock. So in that way they are related. You should wait for the master clock to be stable before releasing the reset. This will depend on your system design. Once the master clock is stable AND you release the reset then it will run the initialization code, the 8 instructions at the MCLK rate. So the direct answer to your question is that the reset is not dependent on MCLK. It is dependent on the internal power domains being stable. Just hold the reset low until your MCLK source is stable, then release the reset. If they are all running off of the same power domain then this should all happen around the same time.

    2) The internal reset is complete only after all the power supplies are good and the reset pin has gone high. There is no further delay. I suppose there is a delay for a flop or two to change, which will be in the single digit nanoseconds.

    The wait for the initialization is 8 cycles of the MCLK is much longer. So if you are using 12.288MHz each cycle is ~81ns. So if you were to wait for 9 instead of 8 cycles you will allow for more than enough time for the internal reset line to go high. If you are calling it this closely, then you should also calculate the time of flight for the reset signal to get to the DSP from the controller and allow for the rise time of the signal. Normally you simply add a little time and you will be fine. The time for all this to happen is very small compared to the time you have to use to boot up the part after all the resets are high and the MCLK and power supplies are all valid. The time for 8 MCLK cycles is 651 ns. So waiting 1 us would suffice.

    Dave T

  • Hi Dave,

    Thanks for detailed information.

    I have an additional question.

    I think there is a period that the reset pin is "don't care" state after turning on the power.

    Can you disclose that "don't care" period?

    It is necessary information to configure system startup in the shortest possible time.

    Thanks and Regards,

  • 0
    •  Analog Employees 
    on Feb 4, 2019 7:10 PM over 2 years ago in reply to takumi3952

    Hello takumi3952,

    This is shown in the Figure 14 diagram. Basically, until the power has come up and stabilized and the internal level shifters start functioning, then the master clock is allow to reach the PLL. At that point the state of the reset pin matters. It could be high or low before that point.

    The biggest variable in all this is the external power supplies and the external caps, how long does it need to come up to min voltage? Our reset generator waits a minimum of 140ms, typical 240ms. ADM811,That is rather long but it allows for time for power to stabilize.

    I have spoken with the engineer who worked on this part and he says as soon as the power is stable it only takes nanoseconds for these signals to propagate through the part.

    Since you are asking for an exact time I cannot give that to you because it depends on external factors. I suppose the best answer for your system would be to study the rise of the power supplies in the system once it is built and all the other parts of the system is in place. Look at the scope traces and see if the power comes up clean or does it bounce? Look at it over many attempts and then see if there is a reasonable number to use to release the reset and start the booting process. I am pretty sure your system will have a controller that is always on and will gate the power to the DSP.

    Dave T

Reply
  • 0
    •  Analog Employees 
    on Feb 4, 2019 7:10 PM over 2 years ago in reply to takumi3952

    Hello takumi3952,

    This is shown in the Figure 14 diagram. Basically, until the power has come up and stabilized and the internal level shifters start functioning, then the master clock is allow to reach the PLL. At that point the state of the reset pin matters. It could be high or low before that point.

    The biggest variable in all this is the external power supplies and the external caps, how long does it need to come up to min voltage? Our reset generator waits a minimum of 140ms, typical 240ms. ADM811,That is rather long but it allows for time for power to stabilize.

    I have spoken with the engineer who worked on this part and he says as soon as the power is stable it only takes nanoseconds for these signals to propagate through the part.

    Since you are asking for an exact time I cannot give that to you because it depends on external factors. I suppose the best answer for your system would be to study the rise of the power supplies in the system once it is built and all the other parts of the system is in place. Look at the scope traces and see if the power comes up clean or does it bounce? Look at it over many attempts and then see if there is a reasonable number to use to release the reset and start the booting process. I am pretty sure your system will have a controller that is always on and will gate the power to the DSP.

    Dave T

Children
  • Hi Dave,

    Thanks for your reply.

    If it is not SELFBOOT, what timing should we start toggle the SS/ADDR0 three times?

    Thanks and Regards,

  • 0
    •  Analog Employees 
    on Feb 8, 2019 3:09 PM over 2 years ago in reply to takumi3952

    Hello Takumi3952,

    Apply power and wait for it to be stable.

    Apply Master Clock and wait for it to be stable.

    Release the Reset pin.

    Wait for at least 8 clock cycles for the initialization code.

    Start the toggles.  

    Do not toggle faster than the incoming master clock.

    Dave T

  • Hi Dave,

    Thank you always.

    Let me continue the discussion a little more.

    After release the reset pin, wait 8 cycles and start the toggle.

    I understand this, but do not we have to wait for the PLL to lock up?

    When considering the startup sequence in the shortest,

    is there any period that must be secured?

    Thanks and Regards,

  • 0
    •  Analog Employees 
    on Feb 22, 2019 2:01 PM over 2 years ago in reply to takumi3952

    Hello takumi3952,

    You have been asking about when you can start communicating with the part and that is what I answered. When you start communicating, the first thing that must be done is to program the PLL registers and set the input to the PLL. You cannot start programming the rest of the part until the PLL is locked and providing clocks to the rest of the part.

    So you program the PLL and either wait around 11ms for the PLL to lock or you can poll the lock bit to see if it is locked. Once it is locked you can proceed with the rest of the procedure. Polling is the faster way because the PLL is usually locked well before the maximum time of 10.666 ms we quote in the datasheet. So by polling you can shave off several milliseconds.

    This is all detailed in the example system initialization register write sequence in the datasheet. (Table 19 in Rev 0 datasheet)

    Dave T

  • Hi Dave,

    Thanks for your reply.

    There is a following description in the power up sequence of datasheet.

     "Each power supply domain has its own power-on reset (POR) circuits (also known as power OK circuits) to ensure that the level shifters attached to each power domain can be initialized properly."

    I should need to wait for the initialization of the level shifter and the time spent on POR?

    Thanks and Regards,