FSK Modem

Hello LA6NCA,

I need to know which SigmaDSP processor you are using. Can you attach your project as well? This way I can just add to it.

The only small question I have is that when there is no signal, then it will only be noise and the output of the comparator will be switching back a forth with changes in the noise.

I think there should be a gate of some sort. A squelch in the radio world. Only the 1160 Hz needs to be shut off. If that level is at zero then any noise on the 1000 Hz input will only keep the output at zero anyway.

Dave T

Thank you KJBob for ZIP info.
RTTY.zip

Need a quick comparator on the output of the two filters. And a digital output to a GPIO pin.
(Has worked mostly with audio and not GPIO before.)
:-)

     Hello Helge,

     Here's a basic setup which compares the two filter outputs:

 The Peak Envelope blocks (1) act as full-wave rectifiers or AM detectors -- they measure the filter outputs.  The ABCD Comparator blocks (3) compare their a and b inputs.  If the a input is larger, the block outputs its c input.  If the b input is larger, the d signal is output.  DC levels feed the c and d inputs via aliases (2).

     Looking at your modulation scheme -- switching between the mark and space oscillators causes jumps in the resulting waveform.  Instead, use one VCO driven to produce the needed frequencies.  It's not hard to set up this way and I can help if you would like.

     Best regards,

     Bob

RTTY-2.zip

Thanks for the interesting answer KJBob.
This was wonderfully good.
I've learned some important things here.
Thank you for adding the zip file.

Yes you are right about that modulator.
I tested it and it didn't work.
I had to make an analogue mux outside the DSP.
If you have a solution to this, I would have been very happy about it.

Regards Helge Fykse

     Hello Helge,

     What's not working with your modulation scheme?  It appears to be in order -- you even remembered to use Buffer Gates to feed your MUX control inputs with integers (28.0 format).   If you're using the ADAU1701MINIZ evaluation board and expecting output at the board's 1/8" jack, choose DAC2 and DAC3 rather than DAC1 and DAC2.  The board hardwires the latter DAC outputs to its built-in amplifier instead.   You need not run an external MUX -- switching between two signals via GPIO control is very workable in SigmaDSP.

     As I had described above, a VCO-based modulation scheme prevents discontinuities in the modulated waveform at input bit changes.  As this Wikipedia article describes, this reduces sideband energy and makes demodulation easier.  The project attached below includes an example VCO-based modulator.

     With a full 1.0 input, the VCO outputs its highest frequency, Fs/2 (24 KHz at the default 48K sample rate).  Other inputs are proportional -- so to get the space frequency of 1000 Hz, we input 1000 / 24000 = 0.04167.  To get the higher mark frequency, simply add the difference in the frequencies (160 Hz) divided again by 24000, which is 0.00667.  You see from the schematic how this is added when the bit input (either from GPIO or the pulse generator I added for a test) equals one.  Because the FSK output always comes from the same VCO without switching, mark-space transitions cause no transients.

    The rest of the attached project demonstrates a possible alternative FSK demodulator.  Instead of comparing the output of two filters, it works by phase-locking another VCO to the input FSK signal.  As this phase-locked loop tries to track the input FSK signal, the VCO input goes up and down with the input frequency -- thus a comparator connected here provides the demodulated ones and zeros.  I'm not sure if this works any better than the filter-based FSK demodulator, but it's fun to play with.  With the circuit running on a ADAU1701MINIZ board and the built-in 50 Hz pulse generator for the input to the modulator, the demodulated signal looks rather good, as shown below:

     Here's how the PLL works:  Multiplier X1 serves as a phase detector by multiplying the input signal with the VCO output.  Its output averages positive if the two signals are in-phase, negative if out-of-phase, and zero when they are 90 degrees apart.  The first-order filter does the averaging, which then adds to the VCO input.  The clipper sets the VCO's frequency range to cover the mark and space frequencies with some room to spare.  With no input FSK signal at all, the VCO sits at the middle frequency set by source DC1.  With signal, the multiplier output tends to pull the VCO higher or lower to match the incoming frequency. 

    The first-order filter along with Gain 1 form the PLL's loop filter.  Adjust the cutoff frequency, filter gain, and Gain 1 for best performance (I only tweaked them until the thing started working).

This demonstration PLL demodulator lacks a squelch so you'll need to add one.  And both the PLL and the filter-based demodulators could likely benefit from adding some hysteresis to their comparators.  This can be done the same way one might add hysteresis to a comparator IC.  And you won't burn your fingers on a hot soldering iron doing it!

     Best regards,

     Bob

FSK-PLL-demod.zip

     Hello Helge,

     What's not working with your modulation scheme?  It appears to be in order -- you even remembered to use Buffer Gates to feed your MUX control inputs with integers (28.0 format).   If you're using the ADAU1701MINIZ evaluation board and expecting output at the board's 1/8" jack, choose DAC2 and DAC3 rather than DAC1 and DAC2.  The board hardwires the latter DAC outputs to its built-in amplifier instead.   You need not run an external MUX -- switching between two signals via GPIO control is very workable in SigmaDSP.

     As I had described above, a VCO-based modulation scheme prevents discontinuities in the modulated waveform at input bit changes.  As this Wikipedia article describes, this reduces sideband energy and makes demodulation easier.  The project attached below includes an example VCO-based modulator.

     With a full 1.0 input, the VCO outputs its highest frequency, Fs/2 (24 KHz at the default 48K sample rate).  Other inputs are proportional -- so to get the space frequency of 1000 Hz, we input 1000 / 24000 = 0.04167.  To get the higher mark frequency, simply add the difference in the frequencies (160 Hz) divided again by 24000, which is 0.00667.  You see from the schematic how this is added when the bit input (either from GPIO or the pulse generator I added for a test) equals one.  Because the FSK output always comes from the same VCO without switching, mark-space transitions cause no transients.

    The rest of the attached project demonstrates a possible alternative FSK demodulator.  Instead of comparing the output of two filters, it works by phase-locking another VCO to the input FSK signal.  As this phase-locked loop tries to track the input FSK signal, the VCO input goes up and down with the input frequency -- thus a comparator connected here provides the demodulated ones and zeros.  I'm not sure if this works any better than the filter-based FSK demodulator, but it's fun to play with.  With the circuit running on a ADAU1701MINIZ board and the built-in 50 Hz pulse generator for the input to the modulator, the demodulated signal looks rather good, as shown below:

     Here's how the PLL works:  Multiplier X1 serves as a phase detector by multiplying the input signal with the VCO output.  Its output averages positive if the two signals are in-phase, negative if out-of-phase, and zero when they are 90 degrees apart.  The first-order filter does the averaging, which then adds to the VCO input.  The clipper sets the VCO's frequency range to cover the mark and space frequencies with some room to spare.  With no input FSK signal at all, the VCO sits at the middle frequency set by source DC1.  With signal, the multiplier output tends to pull the VCO higher or lower to match the incoming frequency. 

    The first-order filter along with Gain 1 form the PLL's loop filter.  Adjust the cutoff frequency, filter gain, and Gain 1 for best performance (I only tweaked them until the thing started working).

This demonstration PLL demodulator lacks a squelch so you'll need to add one.  And both the PLL and the filter-based demodulators could likely benefit from adding some hysteresis to their comparators.  This can be done the same way one might add hysteresis to a comparator IC.  And you won't burn your fingers on a hot soldering iron doing it!

     Best regards,

     Bob

FSK-PLL-demod.zip