Post Go back to editing

ADAU1978 configuration


 I am going to use ADAU1978 audio codec. I have 3 MICs connected to 3 of the ADCs on the codec. I use I2C interface between the codec and STM3F407. What are the register settings that needs to be done?

I will be using the ADC as master. Also, I have a crystal of 12.288 Mhz which will be the master clock.Please help me with register settings.

  • I have done a register setting as follows:


    0x00                                     0x01

    0x01                                     0x40

    0x04                                      0x37

      0x05                                     0x04

      0x06                                      0x01

      0x07                                        0x10

      0x08                                       0x32

      0x09                                        0xF0

      0x0A                                        0xA0

      0x0B                                           0xA0

      0x0C                                        0xA0

    0X0D                                           0xA0

      0x0E                                          0x02

      0x19                                               0x00

      0x1A                                           0x00

    please confirm the same.

  • Hello niyathi08!,

    You made no mention of what the sample rate is and what serial format you require.

    0x01                                     0x40

    With 12.288MHz MCLK then you need to set this for 256x fs. So 0x41 should be the setting.

    0x05                                     0x04

    So you are setting this for 192kHz fs with I2S as your serial format. If this is what you need then this is correct.

    0x06                                      0x01

    This is set to have the ADC be the master. This is correct. The rest of the format settings are correct for standard I2S.

    0x1A                                           0x00

    This register is for control of the DC offset present on all ADCs. If this is a standard audio application then I would recommend you turn on the High Pass Filters. The cutoff is really low so it has minimal effect on the audio but it saves MIPS in the DSP by having the HPF located on the ADC. It will also help prevent and switching pops when switching signals or muting since there will be no DC offset.

    The other option with this part is to do a calibration at startup to obtain the value of the DC offset. Then in this register you can set it to subtract this DC offset from the output signal. This is good to do if you have an application where you need the ADC to go down to DC so therefore you cannot use the HPF, this allows you to remove this offset and still go down to DC on the output of the ADC.

    So since you mentioned you are using this part with three mics I will assume this is a standard audio application. In addition, microphones themselves can have a high DC offset. So I recommend you turn on the HPF for all channels you are using. Set it to 0x07

    Dave T

  • Hi Dave,

    Thank you for the speedy response. I will set registers accordingly and check. 

     Iam going to use ADAU1978 for standard audio recordings,i.e, i have to record audio using 3 MIC's connected on 3 ADCs. 

    When i use I2C protocol the quad ADC ADAU1978 acts as slave and requires a master (I am using STM32F407) in the system to operate.

    As per the datasheet, the clock source for the PLL can either be MCLKIN pin (master mode) or the LRCLK pin (slave mode). I would like know which would be better to use LRCLK or MCLKIN.

    Suppose i choose, MCLKIN as the clock source for PLL, then I set register 0x01 with he value of 0x41 (Master clock select being 256xfs) and fs=192kHz.

    So serial format that i want is I2S format, now my quad ADC will be the master and my microcontroller should be the slave.

    The microcontroller gives me 4 options under I2S communication :

    Full Duplex master, Full duplex slave, Half duplex master and Half duplex slave.

    So with the above requirements i should be choosing full duplex slave or which among the other options?

    Also, the connections from the Quad ADC to the microcontroller are as follows:

    BCLK-->I2S CLK

    LRCLK -->I2S WS



  • Hello

    MCLKIN is better to use. You will need a clock source of 12.288MHz.

    It must be correlated to the LRCLK and the BCLK. Which means it must be divided down from the 12.288MHz master clock. So supply the ADC with the same master clock.

    I have never heard of full duplex and half duplex being used with I2S. So I have no idea. Generally there is a serial input port and a serial output port. Their directions do not change. Only the clock pins change direction in they are a master or slave. So in that sense they are full duplex I suppose?

    Based on the abbreviations for the pins you listed, the connections seem reasonable. I think they are correct. The I2S_WS needs to be at the sample rate so word sync seems right.

    I2S_CLK I am not certain. This clock needs to be 64 x I2S_WS so that it will clock out each bit.

    Dave T

  • Hi Dave,

    Thank you again. I have made the settings accordingly but when i do an I2S receive i dont get anything but 0x00000000 in my I2S receive buffer. Do you have a sample code which is working? If so could you please share the same.

  • Hello niyathi08,

    I suggest you obtain an oscilloscope and look at the signals. You can check that the frequencies are correct and that the correct clocks are in the correct place. You can even see if there is data. I do not have sample code.

    This old post of mine explains how to take these screenshots and you can see what it should look like.

    You could be banging your head against the wall because of something simple being missing.

    Dave T

  • Hi Dave,

    I have used an oscilloscope to look at the signals. I am having no signals just a straight line. Also, i was checking the PLL CONTROL REGISTER ,Address: 0x01, value written :0x40. I was doing an I2C read polling for checking whether the PLL bit (7th bit of PLL control register ) has acquired lock. But it  is never getting setting to set 1 which means it is not acquiring lock. 

  • Hello niyathi08!

    Keep in mind that the messages are quite fast and fairly short in duration. You have to set the scope to a single trace and trigger off of the clock pin to capture a message. So I assume you were doing that.

    So if you have no messages going out then you need to look at your micro-controller to see why it is not sending out any messages?

    What is strange is that with I2C you generally have an acknowledge from the other device for each message and if you do not get it then an error will be generated. That said, the software has to set the comms port to pay attention to the ACK or lack  of an ACK, (called a NACK). If it does not get an ACK then it will have to deal with the error in some sort of error reporting routine. You can program it to ignore them and continue then you get garbage for data, usually all zeros or 1's.

    So have another look at the comms port. If it really is not putting out anything then the problem is with the software of the controller. I2C is pulled up externally and devices pull the lines down to ground to communicate.

    Dave T

  • Hi Dave,

    I2C is giving me ACK also,the PLL is acquiring lock. I am even getting data on I2S. Now i try to store the I2S data into a .wav file.  But I2S Data stored in .wav file not playing correctly!

  • Hello niyathi08!,

    How are you trying to store this data into a wave file? I assume you are not using SigmaStudio? There is no way to pick up the actual audio stream in SigmaStudio to store it into a file. If you are using a Linux based controller with a memory or disk interface then I suppose you could do it but I have no idea how that is done since that would be a product from a different company. So my basic question is how are you reading the I2S audio data?

    Dave T