ADAU1701 and TI digital AMP rattling noise with LP-filtered signal

Hey folks,

I´ve already done a project with the ADAU1452 and wanted to realize a small 4In4 DSP amplifer. Therefore I´ve moved to the ADAU1701 and a digital TDM input amp from TI TAS6424. I´m using the internal ADCs of the ADAU1701 and one 2-Ch exernal ADC via I²S, process them e.g. for a 3.1 (L/C/R/SUB) configuration and send the digital TDM stream to the TI chip. The ADAU1701 is Master for both input and output according to another thread here:

The settings of the hardware configuration window are:

The PCB is 2-layer 70um with SMD parts in which the bottom layer is alomst only GND. The feedback trace of LRCLK and BCLK output to the input is done directly whereas the connection to the external ADC and AMP contains 33R resistors. The traces are kept as short as possible. On the AMP side MCLK is hard-wired to BCLK (This is a possible operation mode for TDM when no MCLK signal is available according to the TI chip manual)

The first tests have been very promising but I´ve noticed two strange issues with channels that use LP filters in their signal flow:

  • The output at the amplifier itself seems to contain a high frequency/transient component that is audible similar to rattling although there is no other processing active. The level of the noise is relative to the input level and therefore always audible. Please refer the test signal flow below

I´ve bought the EVAL board of the TI amplifier chip to verify that the distortion does not come from the amp. With the EVAL board I don´t have these issues. Then I´ve tried to hook the ADAU1452 EVAL board TDM pins to the TI EVAL board and the transient noise was present again. I found out that when I use a buffer IC like 74HC125 between the DSP and the AMP the noise is gone. I´ve tried to verify with the oszi but I don´t understand why the buffered version is working as it should whereas the direct connection over a 33R resistor (I´ve also tried higher values and even ferrite beans) does "produce" the sound. I´ve already done another project that uses only the ADAU1701 and the TI TAS6424 without the I2S feedback traces and tesetd the same configuration with the same noisy result. The buffered CLK signals seem to have smaller fall/rise times but the raw CLKs look already good for me?

BCLK raw

BCLK buffered

LRCLK raw

LRCLK buffered

SDATA raw

SDATA buffered

raw

buffered

  • Any of the peak limiters (I´ve not tried the RMS yet) produces bad distortion at the output even at low levels. I´ve tried different attack, release paramters but they all distort the sound way before the actual threshold. I don´t know this behavior from the ADAU1452 and I know that the ADAU1701 is not that powerful and more cost-efective. However I assume that this should not be the normal behavior?

Any feedback is highly appreciated! Thanks in advance :-)

PS: I´m using SigmaStudio 4.5 Build 1779

Parents
  • Hello folks,

    I made few other tests and I think that the problems are highly related to CLK jitter. When I look at the oscillator output I can see the CLK signal walking although the trigger of the oscilloscope is set properly. I´ve tried few things to get a workaround with my current dual layer pcb but nothing has really helped:

    • I´ve tried to sieve the supply of the DSP with an external 33R resitor and 47uF ceramic cap
    • I´ve checked the PLL filter parameters. tested to swap the 470R against a 100nF (as recommended by another forum discussion)
    • tested another oscillator type (also 12.288MHz)
    • the external buffer IC workaround works for one test PCB. With another PCB assembly I cannot surpress the noise sound with the 74HC125
    • added small 15nF bypass caps on all supply pins

    I´ve gone throught the suggested layout best practices and made a 4-layer re-design. I hope that the problems have been now accounted but to be honest I´m not very confident because it´s more or less the same schematic. I´ve added lots of bypass caps and tried to isolate the oscillator section from the resuming signals but I´m sceptical that this will solve the problems.

    Any further tips on how to reduce the jitter would be higly appreciated. Thanks a lot!

    -C

Reply
  • Hello folks,

    I made few other tests and I think that the problems are highly related to CLK jitter. When I look at the oscillator output I can see the CLK signal walking although the trigger of the oscilloscope is set properly. I´ve tried few things to get a workaround with my current dual layer pcb but nothing has really helped:

    • I´ve tried to sieve the supply of the DSP with an external 33R resitor and 47uF ceramic cap
    • I´ve checked the PLL filter parameters. tested to swap the 470R against a 100nF (as recommended by another forum discussion)
    • tested another oscillator type (also 12.288MHz)
    • the external buffer IC workaround works for one test PCB. With another PCB assembly I cannot surpress the noise sound with the 74HC125
    • added small 15nF bypass caps on all supply pins

    I´ve gone throught the suggested layout best practices and made a 4-layer re-design. I hope that the problems have been now accounted but to be honest I´m not very confident because it´s more or less the same schematic. I´ve added lots of bypass caps and tried to isolate the oscillator section from the resuming signals but I´m sceptical that this will solve the problems.

    Any further tips on how to reduce the jitter would be higly appreciated. Thanks a lot!

    -C

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