The serial ports on SHARC processors (2136x/2137x/214xx) are designed to work till fCCLK/4 speed. However, the actual maximum allowable SCLK speed depends upon the specific timing requirements and switching characteristics as mentioned in the corresponding data sheet specifically on
1) Frame sync delay and frame sync setup and hold
2) Data delay and data setup and hold
3) SCLK width
Referring to following timings in table 34 of the ADSP-21469 data sheet(page 38)
tSDRE - Receive Data Setup Before Receive SCLK - min 1.9 ns and tDDTE - Transmit Data Delay After Transmit SCLK - max 8.5 ns
For CCLK=450 MHz, assume, fSCLK=fPCLK/4 = 56.25 MHz => tSCLK=17.77 ns => tSCLK width = 8.89 ns
Suppose we want to use ADSP-21469's SPORT as slave transmitter which transfers data to another ADSP-21469's SPORT configured as slave receiver. With tDDTE=8.5 ns, we have only 0.39 ns(8.89-8.5) setup time left which is less than the minimum setup requirement by the ADSP-21469 receiver. This limits the ADSP-21469 SPORT's maximum SCLK to only fPCLK/8 instead of fPCLK/4 for this particular case.
Thus, when using the SHARC SPORT's (specially above fPCLK/8 SCLK speed), it is recommended to refer to the respective data sheet and make sure that no timing specification is violated.