The IIR_SS bit (IIRCTL1 register) completely stores the current biquad states in local memory (writes all the DK1 and DK2 states back into the
internal memory states). This is useful in applications that require fast switching to another high priority accelerator task—a required IIR to FIR
processing transition for example. After resuming these states can be reloaded and IIR processing can be continued.
Having said that, there are following few important points which need to be taken care of when using this feature:
1. Once the save state operation has started, it can’t be stopped even by clearing the IIR_EN or IIR_DMAEN bits. Setting IIR_EN and IIR_DMAEN bits would be complete from the core’s side, but will take effect only after the save state operation is complete. Thus, before trying to disable the IIR accelerator, one must poll the corresponding status bits in the IIRDMASTAT register(refer to the table A-53 at page A-91) to make sure that the save state operation is completed successfully. The latency involved (with no other higher priority DMA ON) due to save state operation is given by the following expression:
For 32 bit mode:
14*N + ((8*M)+2)*N)
For 40 bit mode:
14*N + ((15*M)+2)*N)
where N = number of channels, M = number of biquads per channel
2. A write access to any of the IIR accelerator registers which are loaded by chaining method (such as CPIIR, IIRCTL2 etc. as listed in table 3-20 in the I/O Processor chapter) is not allowed when save state operation is going on. A write access to these registers when the save state operation is ON, might result in blocking of IOP core reads until the save state operation completes. Assume a case where the accelerator is configured to generate the interrupt when all channels are done. Inside the ISR, one wants to disable the accelerator and re-enable it again as shown in the code below:
IIR_DMA_ISR:
*pIIRCTL=0; // Disables the accelerator (clears IIR_EN and IIR_DMAEN bits) without waiting for save state operation to complete
*pCPIIR = <New TCB Address>; //Write access to the CPIIR DMA parameter register
<IOP core read access e.g. r0 = dm(IISPI); > //This IOP access will be blocked till the save state operation is complete.
3. It has to be noted that in case of more than one channel (IIR_NCH>0), the IIR_DMASVDk toggles between ‘0’ and ‘1’ as it starts and completes the save state operation of each channel one by one. Thus, one should not rely only on this bit to become zero to ensure that the save state operation is complete for all the channels. To ensure a graceful completion of the save state operation, one must poll both IIR_DMACPL and IIR_DMASVDk bits and make sure that (IIR_DMACPL OR IIR_DMASVDk) = 0 after the IIR_DMAACDONE bit is set. To minimize the core intervention, the recommended method would be to configure the accelerator to generate an interrupt when the processing of all the channels is complete (IIR_CCINTR bit of IIRCTL1 register is set) and wait till (IIR_DMACPL OR IIR_DMASVDk) = 0 inside the interrupt service routine. To minimize the interrupt service time, the core can perform some unrelated tasks before it starts polling for the save state operation completion. For example, the above code can be modified as follows to ensure graceful completion of the save state operation:
#define SAVE_STATE_COMPLETE (IIR_DMACPL|IIR_DMASVDk)
IIR_DMA_ISR:
<do some unrelated core tasks>
while((SAVE_STATE_COMPLETE&*pIIRDMASTAT)!=0)
{
asm("nop;");
}
*pIIRCTL=0; // Disables the accelerator (clears IIR_EN and IIR_DMAEN bits) without waiting for save state operation to complete
*pCPIIR = <New TCB Address>; //Write access to the CPIIR DMA parameter register
<IOP core read access e.g. r0 = dm(IISPI); > //This IOP access will NOT be blocked till the save state operation is complete.
4. General guidelines to avoid performance loss:
When IIR accelerator is used in a system, disabling the accelerator and re-enabling it by setting and clearing the IIR_EN bit is not recommended unless really required as it reloads the coefficients as well. Clearing and setting the IIR_DMAEN bit should be sufficient most of the times if the coefficients are not going to change. The accelerator has local memory sufficient to store the coefficients for up to 24 channels and 12 biquads each channel. Also, the save state feature is designed for some rare cases where it is really required. To avoid performance loss, one should carefully analyze the system requirements and use the save state feature only if really required.