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SHARC Processors requires membership for participation - click to join
214xx IIR Accelerator - how to use the save state operation ?
214xx processors: pull down resistor at SPI_CLK(DPI3) pin may result in SPI master boot failure
ADSP-21469 DDR2 controller- How to configure bit 0 of the DDR2CTL3 register
ADSP-214xx - Memory Test
ADSP-SC58x FFTA Benchmarks
Example of using I2S PCG and SPORT interrupts
FAQ: Does ADI provide USB VID/PID?
FAQ: Flash read/prgm via JTAG
FAQ: I'm interested in the SHARC processor family but don’t know where to start?
FAQ: Is it possible to program the internal ROM on the SHARC family 2126x, 2136x, 2137x and 2146x Processors?
FAQ: Standard Math Library for SHARC
FAQ: Using the Expert Code Generator (EE-322) and Expert DAI (EE-243) plugins for VisualDSP++ in Windows Vista, Windows 7 and Windows 8
FAQ: Why do the January, 2018 ADSP-214xx anomaly lists look so different?
FAQ: ADSP-21369 EZKit expansion port dimensions
FAQ: How do I debug an application which is not booting properly?
How to configure SRU for using TWI on SHARC processors?
If the breakpoint is anywhere in the area of code that the CRC is being checked on, then there could be a problem.
New SHARC Hardware Reference released
Programming PLL on ADSP-214xx processors
SPI serial flash driver & SAFP python script
The ADSP-21469 datasheet rev 0 shows tMCFDZ (DAT/SIG Output Time to Three-state) parameter to be 15ns. However, MediaLB specs require this value for 1024*fs to be less than 6.1ns. Is this a concern?
What is the difference between ADSP-21371KSWZ-2A and ADSP-21371KSWZ-2B
What is the maximum allowed serial port (SPORT) clock (SCLK) frequency for SHARC processors ?
23 Aug 2018 7:27 PM
4 Jun 2018 5:39 PM
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