Processor : ADSP-2146x
The programmable interrupts the processor supports 19 programmable prioritized interrupts, the highest priority interrupt is P0I while the lowest priority is P18I. The programmable interrupt latch bits (P0I–P5I, P14I–P16I) are controlled through the priority interrupt control registers (PICR). Unlike the core (four software interrupts) these software interrupts can be changed in priority.
By default, programmable interrupts (P0I,P1I ..... P18I) have a higher priority than the core software interrupts (SFT0I–SFT3I).
For more information please refer to the sections "Programmable Interrupt Priority Control" and "Programmable Interrupt Priority Control Registers" in the HRM to understand more about the priorities and procedure.
https://www.analog.com/media/en/dsp-documentation/processor-manuals/ADSP-214xx_hwr_rev1.1.pdf
The SFT's has the lowest priority as per the "Interrupt Vector Tables" section mentioned in the PRM.
Reference link: https://www.analog.com/media/en/dsp-documentation/processor-manuals/ADSP-2136x_2137x_214xx_pgr_rev2.4.pdf