Processor: ADSP-21479
The TX interrupt is triggered when the DMA count reaches zero. However, this does not guarantee that the transmission is complete, nor does it confirm that both the Transmitter Holding Register (THR) and Transmit Shift Register (TSR) are empty.
To ensure the transmission has finished, the user must check that both the THR and TSR are empty inside the Interrupt Service Routine (ISR). This can be accomplished by polling the UARTTEMT bit (BIT_6) in the UARTxLSR register. When the UARTTEMT bit is set, it indicates that the transfer is complete. At this point, the user can safely disable the UART to confirm that all data has been transmitted.