As name suggests this works as a Tiny L1 cache when Cache is off, due to this PFB (Pre-fetch Buffer) is enabled with 8 lines single way to reduce the instruction and data latency.
Tiny cache may cause problem if sharing non-constant data between SHARC cores because, for example a value written on core 2 may not be flushed to memory before accessed by core 1 or core 1 may read a stale cached value.
Invalidation:
Disabling the PFB by masking the DPORT_PFB_EN bit in SYSCTRL will resolve this issue but there is a performance impact to doing this.
An alternative approach would be to manually invalidate the PFB cache(Tiny Cache) in read core, before the read by setting the invalidate prefetch buffer bit (CMMR_SYSCTL.PFB_INVAL = 1) and then clearing it (CMMR_SYSCTL.PFB_INVAL = 0). Also, it would seem like a good idea to insert a sync instruction after the write which is in another core. The PFB is invalidated upon core reset.
Below is the pseudo code for reference.
/----------------------------------------------/
Read_Core1.c
int main(int argc, char *argv[])
{
/**
* Initialize managed drivers and/or services that have been added to
* the project.
* @return zero on success
*/
adi_initComponents();
/**
* The default startup code does not include any functionality to allow
* core 1 to enable core 2. A convenient way to enable
* core 2 is to use the adi_core_enable function.
*/
adi_core_enable(ADI_CORE_SHARC1);
do
{
// manually invalidate IPORT and DPORT PFB if data caches are disabled
*pREG_CMMR_SYSCTL |= BITM_CMMR_SYSCTL_PFB_INVAL;
*pREG_CMMR_SYSCTL &= (~BITM_CMMR_SYSCTL_PFB_INVAL);
} while(!shared_data); // Read shared_data
}
/----------------------------------------------/
Write_Core2.c
extern volatile int shared_data;
int main(int argc, char *argv[])
{
/**
* Initialize managed drivers and/or services that have been added to
* the project.
* @return zero on success
*/
adi_initComponents();
shared_data = 0x9; // Write shared_data
asm volatile("sync;"); // Add sync after write
while(1);
}
/----------------------------------------------/
NOTE: Explicitly invalidate the prefetch buffer, after range-based invalidation, write-back, or both, by setting the invalidate prefetch buffer bit.