Flash read/prgm via JTAG

Question: I have a board containing a ADSP-21161 SHARC On the board are > Flash mem for the SHARC FW as well as SDRAM The board contains a legacy JTAG (2x7 pin) interface. I wish to read the FW on the flash via the JTAG interface Which equipment and Software do I require to do this? ================================= Answer: You can refer the below EE note and the associated codes: https://www.analog.com/media/en/technical-documentation/application-notes/EE355.pdf https://www.analog.com/media/en/technical-documentation/application-notes/EE355v01.zip You can use our emulators ICE-1000/ICE-2000. Please refer the below FAQ about ICE-1000/ICE-2000 https://ez.analog.com/docs/DOC-11221 Please find the product page of ICE-1000/ICE-2000 https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/emulators.html#eb-overview

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SHARC Processors

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+214xx IIR AcceleratorL FAQ
+214xx processors: FAQ
Accessing SPI Flash with more than 128Mb *LDR
+ADSP-21364: FAQ
+ADSP-21369: FAQ
+ADSP-21371: FAQ
+ADSP-21469: FAQ
+ADSP-21479: FAQ
+ADSP-21489: FAQ
+ADSP-2148x: FAQ
+ADSP-SC58x: FAQ
ADSP-SC594 - DDR Sweep Test
+ADSP-SC5xx/215xx Boot with CRC32
+Breakpoint: FAQ
+Debug an Application: FAQ
Do we need to use Static Voltage Scaling (SVS) to operate the ADSP-2148x in 450MHz?
Does ASRC TDM mode used the opposite clock edge as in other modes such as I2S for sampling and driving the inputs and outputs?
elfloader Commands for Generating an ADSP-SC594 single and Multicore Loader Stream.
Example commands for generating Secure loader streams for SC59x and 2159x processors
Example for FIR Decimation and Interpolation Sampling using ADSP-21569
Example for Octal SSL Booting using SC594
Example for SPI Slave Boot mode for ADSP-21489 using CCES
Example to issue a system reset when watchdog expiration event occurs
Features of OTP over Secure Booting
FIR Accelerator performance degrades when modifier(ADI_FIR_CHANNEL_INFO structure) are other than 1
How to configure DAI pins as GPIO?
How to enable all the SPORTs (0-7) at the same time in ADSP-SC59x/ADSP-2159x?
How to program the system core FLAG pins in ADSP-2156x
How to properly invalidate the Pre-Fetch Buffer?
How to read the status of SYS_BMODE pins using software for ADSP-21569 and ADSP-21593?
How to select PCG Input source for ADSP-SC59x
+I2S PCG: FAQ
Is it feasible to transition the pins mode from SPI functionality to GPIO after booting the DSP from SPI master?
Is it possible to boot the program code from HyperFlash and execute it in HyperRAM?
Is it possible to recover the information from Loader(LDR) or executable(DXE) files.
Is it possible to use the ADSP-21569 init code for ADSP-21565?
Is it possible to use the same pin as SPI_SS as a GPIO interrupt trigger when using SPI simultaneously?
-JTAG: FAQ
- Flash read/prgm via JTAG
MTM DMA transfer on ADSP-21489
Output L and R channels are reversed in AD1939_I2S_Sampled_Based_Talkthru BSP code for ADSP-21469
Pre-boot time for ADSP-2156x and ADSP-SC59x/ADSP-2159x
Second stage loader example for SC594
+SHARC family: FAQ
+SHARC processor: FAQ
SPI Chain DMA example for ADSP-21489
SPI example for ADSP-21369
SPI Master to Slave loopback communication in ADSP-21569
+SPI serial flash driver: FAQ
SSL example for ADSP-21593
+SSL: FAQ
Support for Automatic Device Detection in Secure Booting
Tiny Cache in ADSP-2156x and ADSP-SC59x/ADSP-2159x
+USB VID/PID: FAQ
Value of DDR reference resistor (DMC0_RZQ) and ZQ for SC594
What is the behavior of Circular Buffer mode?
What is the difference between “adi_signtool.exe” and “signtool.exe”? Does “adi_signtool.exe” only be used with GLXP?
What is the effect of enabling/disabling the ADI_SPORT_BLOCKING_MODE
What is the maximum supported clock frequency in Linkport DDR mode for SC594
What is the priority of programmable interrupts in comparison to core software interrupts (SFT0I–SFT3I)?
What is the Reset value of PADS_PCFG.FAULT_DIS bit ADSP-2159x and SC59x processors
What is the SPU_ID for EMDMA0/1 channels in ADSP-SC594/21594
Where can I find the 2Mbits memory map configuration for ADSP-21488 automotive parts?
Why does the UART TX interrupt trigger before THR and TSR are empty?
Why is it mandatory to send 1024-byte blocks during Secure SPI slave boot?