Attached is the PCG example code for ADSP-21489. This code is configured to synchronize the "rising edge of frame sync" with "falling edge of BCLK". Please find the attached images for reference.
One method is to use the FSxPHASE_HI bit in the PCG_CTLx0 register. Phase shift is a frame sync parameter that defines the phase shift of the frame sync with respect to the input clock of the same unit. This feature allows shifting of the frame sync signal in time relative to the clock input signal.
Please note that phase shifting is specified as FSx PHASE_HI bit field (bits 29–20) of the a 2 x 10-bit divider value in the PCG_CTLxO register and in the FSxPHASE_LO bit field (bits 29–20) of the PCG_CTLx1 register.
Other way is to invert your clock signal is to route them to DAI_PB19 or DAI_PB20 pin, which has the pin invert feature. It can be enabled using SRU_PIN3 register.
