Choosing PCLK as input to PCG

How do I specify / configure the PCLK (Peripheral Clock) as the input to the PCG and route it through SRU?

  • In order to route PCLK as input to the PCG you need to set CLKA_SOURCE_IOP bit in the PCG_SYNCx register. By doing this PCLK is used as the input for deriving the clk and fsync from the PCG. If this bit is not set, then the external clk is used as PCG input. This is given in register description section of PCG_SYNC register and also under Clock Output Section of PCG chapter in ADSP-21368 Hardware Reference Manual.
    Things to do, to verify this is working are
    1. Set the CLKA_SOURCE_IOP bit in the PCG_SYNCx register.
    2. Route the PCG clk/FS output to a DAI pin and monitor to see if you can get the clk/FS.

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