Is it normal to see two extra frame syncs after the transmission of last data when the receiver is configured for generating clock and FS?
Yes, this is normal. This is because while transmission the Shift register is the last stage of transmission. But while receiving, shift register is the first stage of reception,then it needs to be shifted into the buffer register and moved into the internal memory. So after the transmitter transmits the last word, still two more words need to be shifted in, before all the words are stored in the memory. You can see that if the clock is generated by the transmitter does not produce two extra cycles.