SHARC Processors

Q&A Extra Frame syncs in Serial Port Receive, Master mode

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Extra Frame syncs in Serial Port Receive, Master mode

ADIApproved

on Apr 15, 2009

Is it normal to see two extra frame syncs after the transmission of last data when the receiver is configured for generating clock and FS?

Tags: Audio Signal Processors adsp-21365 sharc serial_port frame_sync adsp-21366 receiver frame adsp-21364 sport SHARC Audio Processors/SoCs Show More

0 ADIApproved

on Apr 15, 2009 3:31 PM
Yes, this is normal. This is because while transmission the Shift register is the last stage of transmission. But while receiving, shift register is the first stage of reception,then it needs to be shifted into the buffer register and moved into the internal memory. So after the transmitter transmits the last word, still two more words need to be shifted in, before all the words are stored in the memory. You can see that if the clock is generated by the transmitter does not produce two extra cycles.
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0 EZAdministrator
on Apr 29, 2019 6:46 AM
This question has been closed by the EZ team and is assumed answered.
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