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How to distinguish SPORT interrupts from different channels?

I am using SPORT dma with chaining on the ADSP-21369 processor. For example, I have channels

SPORT1A and SPORT1B both configured as transmitters. DMA chaining is enabled for both

channels, so that they toggle back and forth between dma transmit buffers. However, since there

is only one SPORT1 interrupt and not separate interrupts for the SPORT1A and SPORT1B

channels, when I get a SPORT1 interrupt how can I tell which channel caused the interrupt? Are

there bits in a register I can check to find out which channel caused the interrupt? Also, is

there a bit I need to clear once an interrupt occurs, in order to keep the interrupt from recurring

and to enable the next interrupt? Thanks very much for any help ... Richard

  • Hi Richard,

         The SPMCTLx register has the status bits(24-31) for the DMA operation. These bits are applicable for to all the SPORT modes. The SPMCTL0 register has the DMA status and DMA chaining status for SPORT0A, SPORT0B , SPORT1A and SPORT1B channels. The  SPMCTL1 register also has the same status bits. These bits indicate which channel DMA is completed and which is running. Please refer Figure A-19 on  page A-41 of the ADSP-21368 HRM for more details.

    But these bits may not be useful for the case where the DMA chaining runs continuously. I would like to add the following points for this case from the application point of view:

    1. Both the channels A and B use the same clock and Frame sync for the data transfer. In the application if the same buffer size is used then both the DMAs will be completed almost at the sametime. You need not have to check which
    channel generated the interrupt.

    2. In case you use different buffer size for both the channels then the channel with the lower count would generate the interrupt first. Inside the ISR you can use a software flag to keep track of which channel generated the interrupt.


    Best Regards,

    Jeyanthi


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