I've got a question about the clearing interrupts for UART_TX, and UART_RX in DMA mode.
Is is necessary read the DPI_IRPTL register to clear those interrupts?
Or, what is necessay to do?
*pPICR2 &= ~(0x1F); //Clear DAI2I interrupt from P12 *pPICR2 |= (0x15); //Sets the UART0 transmit interrupt to P12 interrupt(SIG_P12,UART0_TX_Isr);
*pPICR3 &= ~(0x1F); //Clear SPIB interrupt from P18 *pPICR3 |= (0x14); //Sets the UART1 receive interrupt to P18 interrupt(SIG_P18,UART1_RX_Isr);
Thanks for answer
I've asked due to confusion
in Table B-2. Interrupt Vector Addresses in ADSP-21368 SHARC Processor Hardware Reference.pdf
is written that
Programmable interrupt 12 (DAI2)
is in register LIRPTL
Programmable interrupt 18 (SPIB)
is in LIRPTL too.
Why do I need to read register IRPTL?
Thank you for excellent answer.
Yes, it's recommended to clear the UART RX/TX DMA completion interrupt latched in to the DPI_IRPTL register by reading this register inside the ISR.
Sorry but I am very clear about the confusion you mentioned about as DAI2 and SPIB interrupts have no direct relation with the DPI or UART interrupts. Also, reading the DPI_IRPTL register is inside the DPI ISR is a general (not very specific to UART) recommended procedure to clear all the latched DPI interrupts to avoid servicing the ISR again and again even without a valid interrupt. Please note the following statement at page 6 of the application note EE-305 :
"Unlike other interrupts, the DAI interrupt is not cleared automatically inside the DAI interrupt service routine. Once latched, the interrupt remains latched until the latch status is cleared explicitly by reading the DAI interrupt latch register. DAI interrupts are cleared by reading the DAI interrupt latch register. If this does not occur, the program will keep sequencing to the DAI interrupt service routine every time after coming out of it."
This statement is applicable for DPI interrupt also.
Please also note that instead of using DPI interrupt, you may as well map the UART Tx/Rx interrupts to any of the programmable interrupts using PICRx registers. In that case, you wouldn't need to explicity clear the interrupt latch in the ISR.
Hope this helps.