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Using an Emulator to defeat watchdog

Almost all the embedded designs I take credit for detect the presence of, or the operation of an emulator to defeat a watchdog circuit. Obviously when stepping through code, having the processor reset is not much help.
So, for the SHARC processors (ADSP-21065L & ADSP-21160N), the ICE TRST signal is used which goes high when the test port is active and the DSP core paused. Has anyone else done this, what has been your experience - or can you recommend a better way (by the way jumpers and switches or any miss configurable parts are not allowed).
Anyone know a down side to this, perhaps newer processor issues?

 

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  • Hi Deepa,

    This is the way my watchdog circuit works:

    I have an external watchdog counter, this is hardware and part of an FPGA.

    The watchdog counter is reset to 0 by:

    1)      The DSP master reset going low

    2)      By the emulators TRST line going high. I have a 4K7 pull down resistor.

    3)      A transition on FLAG3 a general purpose DSP I/O line.

    Under normal operation the counter is reset to 0 by software using the FLAG3 signal.

    The counter has 2 thresholds:

    1)      After 100mS, the first threshold increments a violation counter in the FPGA, asserts a DSP NMI (reports the exception and does some task scheduler checking - stack overflow etc.)

    2)      After a total 200mS, the second threshold asserts DSP reset.

    When the DSP boots, the code can query the FPGA to read some status flags and registers – there are many, here’s 4 . . .

    1)      Manual reset

    2)      Power on reset

    3)      Stack overflow

    4)      Watchdog timeout

    The boot cause status is displayed on boot-up.

    So when an emulator is connected to the JTAG port and TRST is high, the watchdog counter is reset to 0 to allow debugging.

    This works fine on a DUAL ADSP21065L and a similar or more basic version for the ADSP21160N.

    So, if the basic JTAG operation for the ADSP21065L is the same as the ADSP21160N i.e. TRST works in the same way, then the circuit should work ok.

    Regards

    Steve

    Stephen Wells

    Electronics MTS | Implant AGS | Applied Materials

    Office 512-272-3137

    The content of this message is Applied Materials Confidential. If you are not the intended recipient and have received this message in error, any use or distribution is prohibited. Please notify me immediately by reply e-mail and delete this message from your computer system. Thank you.

      • Save a tree. Please don't print this e-mail unless needed.

    From: DeepV analog@sgaur.hosted.jivesoftware.com

    Sent: Monday, October 03, 2011 5:04 AM

    To: Steve Wells

    Subject: New message: "Using an Emulator to defeat watchdog"

    Analog Devices EngineerZone<http://ez.analog.com/index.jspa>

    Using an Emulator to defeat watchdog

    reply from DeepV<http://ez.analog.com/people/DeepV> in SHARC Processors - View the full discussion<http://ez.analog.com/message/33422#33422

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  • Hi Deepa,

    This is the way my watchdog circuit works:

    I have an external watchdog counter, this is hardware and part of an FPGA.

    The watchdog counter is reset to 0 by:

    1)      The DSP master reset going low

    2)      By the emulators TRST line going high. I have a 4K7 pull down resistor.

    3)      A transition on FLAG3 a general purpose DSP I/O line.

    Under normal operation the counter is reset to 0 by software using the FLAG3 signal.

    The counter has 2 thresholds:

    1)      After 100mS, the first threshold increments a violation counter in the FPGA, asserts a DSP NMI (reports the exception and does some task scheduler checking - stack overflow etc.)

    2)      After a total 200mS, the second threshold asserts DSP reset.

    When the DSP boots, the code can query the FPGA to read some status flags and registers – there are many, here’s 4 . . .

    1)      Manual reset

    2)      Power on reset

    3)      Stack overflow

    4)      Watchdog timeout

    The boot cause status is displayed on boot-up.

    So when an emulator is connected to the JTAG port and TRST is high, the watchdog counter is reset to 0 to allow debugging.

    This works fine on a DUAL ADSP21065L and a similar or more basic version for the ADSP21160N.

    So, if the basic JTAG operation for the ADSP21065L is the same as the ADSP21160N i.e. TRST works in the same way, then the circuit should work ok.

    Regards

    Steve

    Stephen Wells

    Electronics MTS | Implant AGS | Applied Materials

    Office 512-272-3137

    The content of this message is Applied Materials Confidential. If you are not the intended recipient and have received this message in error, any use or distribution is prohibited. Please notify me immediately by reply e-mail and delete this message from your computer system. Thank you.

      • Save a tree. Please don't print this e-mail unless needed.

    From: DeepV analog@sgaur.hosted.jivesoftware.com

    Sent: Monday, October 03, 2011 5:04 AM

    To: Steve Wells

    Subject: New message: "Using an Emulator to defeat watchdog"

    Analog Devices EngineerZone<http://ez.analog.com/index.jspa>

    Using an Emulator to defeat watchdog

    reply from DeepV<http://ez.analog.com/people/DeepV> in SHARC Processors - View the full discussion<http://ez.analog.com/message/33422#33422

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