Using an Emulator to defeat watchdog

Almost all the embedded designs I take credit for detect the presence of, or the operation of an emulator to defeat a watchdog circuit. Obviously when stepping through code, having the processor reset is not much help.
So, for the SHARC processors (ADSP-21065L & ADSP-21160N), the ICE TRST signal is used which goes high when the test port is active and the DSP core paused. Has anyone else done this, what has been your experience - or can you recommend a better way (by the way jumpers and switches or any miss configurable parts are not allowed).
Anyone know a down side to this, perhaps newer processor issues?

 

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  • Hi Deepa,

    I must be on my 5th design using various SHARC processors, this time I am upgrading an older legacy design which uses the old ADSP21160N part (we want to keep the software as is for now).

    In all my previous designs I have used an external watchdog counter (ASSP or PLD/FPGA) and so it has been convenient for me to use the JTAG emulator port TRST line to hold the watchdog timer reset whilst using the debugger (EZICE). I suspect later DSP variants with internal watchdog do a similar thing.

    Anyway, this is the first time using this older 21160 part and just wanted to double check that the JTAG timing is friendly with this kind of feature and perhaps then to recommend it as an alternative to using test links.

    Regards

    Steve

    Stephen Wells

    Electronics MTS | Implant AGS | Applied Materials

    Office 512-272-3137

    The content of this message is Applied Materials Confidential. If you are not the intended recipient and have received this message in error, any use or distribution is prohibited. Please notify me immediately by reply e-mail and delete this message from your computer system. Thank you.

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    From: DeepV analog@sgaur.hosted.jivesoftware.com

    Sent: Monday, September 19, 2011 6:39 AM

    To: Steve Wells

    Subject: New message: "Using an Emulator to defeat watchdog"

    Analog Devices EngineerZone<http://ez.analog.com/index.jspa>

    Using an Emulator to defeat watchdog

    reply from DeepV<http://ez.analog.com/people/DeepV> in SHARC Processors - View the full discussion<http://ez.analog.com/message/32425#32425

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  • Hi Deepa,

    I must be on my 5th design using various SHARC processors, this time I am upgrading an older legacy design which uses the old ADSP21160N part (we want to keep the software as is for now).

    In all my previous designs I have used an external watchdog counter (ASSP or PLD/FPGA) and so it has been convenient for me to use the JTAG emulator port TRST line to hold the watchdog timer reset whilst using the debugger (EZICE). I suspect later DSP variants with internal watchdog do a similar thing.

    Anyway, this is the first time using this older 21160 part and just wanted to double check that the JTAG timing is friendly with this kind of feature and perhaps then to recommend it as an alternative to using test links.

    Regards

    Steve

    Stephen Wells

    Electronics MTS | Implant AGS | Applied Materials

    Office 512-272-3137

    The content of this message is Applied Materials Confidential. If you are not the intended recipient and have received this message in error, any use or distribution is prohibited. Please notify me immediately by reply e-mail and delete this message from your computer system. Thank you.

      • Save a tree. Please don't print this e-mail unless needed.

    From: DeepV analog@sgaur.hosted.jivesoftware.com

    Sent: Monday, September 19, 2011 6:39 AM

    To: Steve Wells

    Subject: New message: "Using an Emulator to defeat watchdog"

    Analog Devices EngineerZone<http://ez.analog.com/index.jspa>

    Using an Emulator to defeat watchdog

    reply from DeepV<http://ez.analog.com/people/DeepV> in SHARC Processors - View the full discussion<http://ez.analog.com/message/32425#32425

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