ADSP-21489 EZ-Board - multiple src in tdm mode

Hi everybody,
i am using a ADSP-21489 EZ-Board. I took the C Block-Based Talkthru 48 kHz example and tried to integrate two sample rate conversions.
What I'd like to do:

- take 48 kHz samples from the 4 RCA jacks, decimate the sampling frequency to 8 kHz
- my existing software takes the 8 kHz samples, outputs samples with 16 kHz
- upsample those to 48 kHz, output to the 8 RCA jacks

I tried to use the SRC1 unit between the ADC and SPORT1 (Rx) and SRC0 between SPORT0 (Tx) and DAC, but sadly I wont get any output...

My SPORT control registers:

    //12.288 MHz SCLK from AD1939
    *pDIV1 = 0x05FF0000;
    *pDIV0 = 0x02FF0000;

    // sport1 control register set up as a receiver in MCM
    // externally generated SCLK1
    *pSPCTL1 =     SCHEN_A | SDEN_A | SLEN24 | IMFS;
   
    // sport0 control register set up as a transmitter in MCM */
    // sport0 control register, SPCTL0 = 0x000C01F0 */
    *pSPCTL0 =     SCHEN_A | SDEN_A | SPTRAN | SLEN24 | IMFS;

    // sport1 receive & sport0 transmit multichannel word enable registers
    *pSP1CS0 = 0x0000000F;    // Set to receive on channel 0-3 on SPORT1
    *pSP0CS0 = 0x000000FF;    // Set to transmit on channel 0-7 on SPORT0

    // sport1 & sport0 receive & transmit multichannel companding enable registers
    // no companding for our 4 RX and 8 TX active timeslots
    // no companding on SPORT1 receive
    // no companding on SPORT0 transmit
    *pMR1CCS0 = *pMT0CCS0 = 0;

    // SPORT 0&1  Miscellaneous Control Bits Registers
    // SP01MCTL = 0x000000E2,  Hold off on MCM enable, and number of TDM slots to 8 active channels
    // Multichannel Frame Delay=1, Number of Channels = 8, LB disabled
    *pSPMCTL0 = NCH7 | MFD1;
    *pSPMCTL1 = NCH7 | MFD1;

   
    // Enable multichannel operation (SPORT mode and DMA in standby and ready)
    *pSPMCTL0 |= MCEA;
    *pSPMCTL1 |= MCEA;

SRU Settings:

    SRU(DAI_PB07_O, SPORT1_CLK_I);   // DAIP17 (RSCLK1) to SPORT1 CLK (CLK)
    SRU(DAI_PB07_O, SPORT0_CLK_I);   // DAIP7 (RSCLK1) to SPORT0 CLK (CLK)

//--------------------------------------------------------------------------
// Route SPI signals to AD1939 Control Port.

    SRU(SPI_MOSI_O, DPI_PB01_I);     //Connect MOSI to DPI PB1.
    SRU(DPI_PB02_O, SPI_MISO_I);     //Connect DPI PB2 to MISO.
    SRU(SPI_CLK_O, DPI_PB03_I);      //Connect SPI CLK to DPI PB3.
    SRU(SPI_FLG0_O, DPI_PB04_I);     //Connect SPI FLAG0 to DPI PB4.
       
//---------------------------------------------------------------------------
// Tie pin buffer enable from SPI peipheral to determine whether they are
// inputs or outputs

    SRU(SPI_MOSI_PBEN_O, DPI_PBEN01_I);
    SRU(SPI_MISO_PBEN_O, DPI_PBEN02_I);
    SRU(SPI_CLK_PBEN_O, DPI_PBEN03_I);
    SRU(SPI_FLG0_PBEN_O, DPI_PBEN04_I);

//---------------------------------
// Connect SRC clock and framesync

    SRU(DAI_PB07_O, SRC1_CLK_IP_I);
    SRU(DAI_PB07_O, SRC0_CLK_OP_I);
   
    SRU(DAI_PB08_O, SRC1_FS_IP_I);
    SRU(DAI_PB08_O, SRC0_FS_OP_I);
   
    SRU(SPORT1_CLK_O, SRC1_CLK_OP_I);
    SRU(SPORT0_CLK_O, SRC0_CLK_IP_I);
   
    SRU(SPORT1_FS_O, SRC1_FS_OP_I);
    SRU(SPORT0_FS_O, SRC0_FS_IP_I);
   
//---------------------------------

//---------------------------------
// Connect SRC1 between ADC -> Sport1, SRC0 between Sport0 -> DAC
   
   
    SRU(DAI_PB05_O, SRC1_DAT_IP_I);            //DAIP5 (DR1PRI) to SRC1 input
    SRU(SRC1_DAT_OP_O, SPORT1_DA_I);    //SRC1 output to SPORT1 DA (RX)

    SRU(SPORT0_DA_O, SRC0_DAT_IP_I);

    SRU(HIGH, PBEN12_I);
    SRU(SRC0_DAT_OP_O, DAI_PB12_I);        //SRC0 output to SPORT0 DA (TX)

SRC Settings:

        *pSRCCTL0 =SRC0_SMODEIN1 | SRC0_SMODEOUT1 | SRC1_SMODEIN1 | SRC1_SMODEOUT1; // TDM In/out, 24bit

        // Enable SRC in a different cycle than setting the configuration
        *pSRCCTL0 |= SRC0_ENABLE | SRC1_ENABLE;

What am I missing?

Thanks in advance,

lyman