ADSP-21261 TDM Codec interfacing

Hi,

I have a custom board with a ADSP-21261 DSP. SPORT01 is connected to A PCM3168 codec, which is configurated as  Master.

24 bit, sampling frequency = 48KHz, BCLK is set to 256*48KHz, FS is generated every 1/48KHz with 50% duty.

I want to use a 8 Channel duplex TDM signal, since the codec supports 6 in and 8 outs.

My current status:

- SRU is set up

- PGC is set as system clock for the codec

- SPCTL0,1 set to SLEN24 and FSR

- SPMCTL01 is set to NCH7, MCEA

- SIG_SP1 interrupt is set and get triggered

First i want to get core driven mode running, what do I have to do in the interrupt? Where are the channelinformation in TXSP0A, RXSP1A?

Where can I get information or examples describing this art of setup?

Regards,

fbalk

  • 0
    •  Analog Employees 
    on Dec 5, 2011 11:10 AM

    Hi,

    The best approach would be to use the DMA chaining mode as being used in the following example code:

    "....\Program Files\Analog Devices\VisualDSP 5.0\214xx\Examples\ADSP-21469 EZ-Board\21469 AD1939 C Block-Based Talkthru 48 or 96 kHz"

    Though it's given for ADSP-21469, similar method can be used for ADSP-21261 also.

    As far as the channel information is concerned, the CHNL(22..16) bits of the SPMCTLxy register provides information about the currently active channel.

    Hope this helps.

    Thanks,

    Mitesh

  • Hi Mitesh,

    thanks for your reply.

    I got some DMA chaining code running, but the codec's output isn't as expected, seems like some bits are shifted or whatever.

    I attached my current code, maybe you'll take a look at it.

    Thanks,

    flbalk

  • 0
    •  Analog Employees 
    on Dec 6, 2011 10:23 PM

    Hi flbalk,

    I haven't looked at the codec data sheet you want to be able to interface. But, I looked at your code.  However, I couldn't see any codec configuration code in it. Could you please mention more about how this codec is configured (SPI/I2C)? Did you already make sure that it is getting configured correctly.

    Also,  for better understanding about the interface, could you please elaborate more about the DSP-Codec H/W connections (may be with a block diagram) and a brief of the software (including the list of the DSP peripherals you will using) you plan to use for this interface.

    As far as SPORT problem is concerned, this may be rather easier to debug once you make sure that you at  least see a valid data being sent by the codec by probing the signal on an oscilloscope.

    Thanks,

    Mitesh

  • Hi Mitesh,

    Sorry I didn't mention the codec is configured by an AVR via i²c. However, my problem seems to be solved, I had to trigger the fs on rising edge.

    I figured out, that SLEN24 and SLEN32 doesn't make any difference, is that possible?

    FYI the codec is wired like this:

    CODEC               SHARC

    DIN           <--   SPORT0_DA

    DOUT        -->  SPORT1_DA

    BCK_DA    --> SPORT01_CLK

       |

       |->BCK_AD

    LRCLKDA    -->  SPORT1_FS

      |

      |->LRCLKAD

    SCKI         <--   PCG_A

    My next step is to configure the SPI slave boot of the SHARC via the AVR.

    Greets,

    flbalk

  • 0
    •  Analog Employees 
    on Dec 12, 2011 9:52 AM

    Hi flbalk,

    Glad to know that your issue is solved. Regarding: "I figured out, that SLEN24 and SLEN32 doesn't make any difference, is that possible?": This statement may not be true generally. Could you please be more specific and mention what do you mean by that with  an example?

    Thanks,

    Mitesh