I am working with an ADSP-21363 SHARC DSP where I use SPORT channels to receive and transmit left-justified audio stream.
SPORT1 (RX) handles the reception of N audio samples (left-justified) through DMA.
SPORT0 (TX) handles the transmission of N audio smaples (left-justified) through another DMA channel.
Both SPORT modules are configured in left justified mode with external frame-sync and samples clocks. The DMA channels are confgure to work in chain mode (double bufferd/ping-pong) DMA.
I have a very specific question regarding the start up of my SPORT/DMA channels. Obviously I can not start the DMA transaction on both SPORT modules synchronously as I need to write into 2 different registers one after another. Normally (as far as I understand) the SPORT/DMA transfer will start on the next rising frame sync edge. Now imagine the following sequence:
(external clock and frame sync running)
T+0 = Enable/start SPORT RX transfer by writing into the configuration register.
T+1 = Rising frame sync edge activates the RX channel (LEFT first).
T+2 = Enable/start SPORT TX transfer by writing into (another) configuration register.
T+3 = The TX channel will wait for the next rising frame sync edge before starting the transmission (LEFT first).
Question: Is it somehow possible that the TX transfer will start on a falling frame sync edge (RIGHT first)? I don't think so but I really need to be sure as I see a LEFT/RIGHT swap on the TX channel from time to time and I am trying to figure out if it's the hardware on rather my processing and copy routines that create the mess.