FPGA & Parallel flash connecting on the AMI

Hi Dotan,

Please see my replies below:

dshambi wrote:

Hi ,

My design incude the ADSP-21469 connecting to an external parallel flash memory-8 bit data bus (RC28F00AM29EWL) and to  FPGA (Cyclone 3) Via the AMI bus ( the FPGA is connected to MS0 and the flash to MS1).
according to the aboved connection i have 2 questions :

1. when i write to the flash for some reason it writes to 2 consecutive addresses for example , if i write to address 0x04000000 the data 0xaa i will read 0xaa from address 0x04000000 and from 0x04000001 , i think its probably a packing problem but i didnt manage to point where i done wrong.

Mitesh>> Could you please attach the simplest code which replicates the problem. As Ajith mentioned, please disable packing (PKDIS) as well and check if you see the same issue.

2. Since the FPGA is connecting to MS0n its internal addresses are common with the DDR2 (that also connected on my board) , i have mange to control the lines of the AMI in that case using the EPCTL Register but i think the adresses is some how shifted for example internal address 0x0020 0000 (with EPCTL , B0SD bit turninig to AMI) supposed to reflect address 0x000000 on the AMI ADDRESS bus is correct or there is another tranlation form the internal memory to the AMI ADDRESS ?

Mitesh>>As mentioned on page 4-17 of the ADSP-214xx HRM Rev 1.0, with PKDIS=0, the address 0x200000 maps to the physical address 0x800000 (left shifted by 2bits). For more details, please refer the HRM.

I will very apperciate your fast respond since this issue is critical to me.

Best regards

Dotan

Thanks,

Mitesh

Hi Dotan,

Please see my replies below:

dshambi wrote:

Hi ,

My design incude the ADSP-21469 connecting to an external parallel flash memory-8 bit data bus (RC28F00AM29EWL) and to  FPGA (Cyclone 3) Via the AMI bus ( the FPGA is connected to MS0 and the flash to MS1).
according to the aboved connection i have 2 questions :

1. when i write to the flash for some reason it writes to 2 consecutive addresses for example , if i write to address 0x04000000 the data 0xaa i will read 0xaa from address 0x04000000 and from 0x04000001 , i think its probably a packing problem but i didnt manage to point where i done wrong.

Mitesh>> Could you please attach the simplest code which replicates the problem. As Ajith mentioned, please disable packing (PKDIS) as well and check if you see the same issue.

2. Since the FPGA is connecting to MS0n its internal addresses are common with the DDR2 (that also connected on my board) , i have mange to control the lines of the AMI in that case using the EPCTL Register but i think the adresses is some how shifted for example internal address 0x0020 0000 (with EPCTL , B0SD bit turninig to AMI) supposed to reflect address 0x000000 on the AMI ADDRESS bus is correct or there is another tranlation form the internal memory to the AMI ADDRESS ?

Mitesh>>As mentioned on page 4-17 of the ADSP-214xx HRM Rev 1.0, with PKDIS=0, the address 0x200000 maps to the physical address 0x800000 (left shifted by 2bits). For more details, please refer the HRM.

I will very apperciate your fast respond since this issue is critical to me.

Best regards

Dotan

Thanks,

Mitesh