FPGA & Parallel flash connecting on the AMI

Hi,

as your question relates to the SHARC ADSP-21469 I have moved this question to the SHARC Processors Community for greater visibility. Please continue the discussion here.

Regards,

Craig.

Hello Dotan,

Regarding your 1st question.

I was also facing same problem in 21489. This is solved by enabling PKDIS bit in AMICTL register.

With PKDIS disabled for each read/write operation from DSP there will be 2/4 read-write cycles to FLASH.

With PKDIS enabled there will be one to one address mapping between physical and logical address and there wont be any 2/4 read-write cycles but some other problem might arise(not sure, will discuss shortly).

Regards,

Ajith

Hi Dotan,

Please see my replies below:

dshambi wrote:

Hi ,

My design incude the ADSP-21469 connecting to an external parallel flash memory-8 bit data bus (RC28F00AM29EWL) and to  FPGA (Cyclone 3) Via the AMI bus ( the FPGA is connected to MS0 and the flash to MS1).
according to the aboved connection i have 2 questions :

1. when i write to the flash for some reason it writes to 2 consecutive addresses for example , if i write to address 0x04000000 the data 0xaa i will read 0xaa from address 0x04000000 and from 0x04000001 , i think its probably a packing problem but i didnt manage to point where i done wrong.

Mitesh>> Could you please attach the simplest code which replicates the problem. As Ajith mentioned, please disable packing (PKDIS) as well and check if you see the same issue.

2. Since the FPGA is connecting to MS0n its internal addresses are common with the DDR2 (that also connected on my board) , i have mange to control the lines of the AMI in that case using the EPCTL Register but i think the adresses is some how shifted for example internal address 0x0020 0000 (with EPCTL , B0SD bit turninig to AMI) supposed to reflect address 0x000000 on the AMI ADDRESS bus is correct or there is another tranlation form the internal memory to the AMI ADDRESS ?

Mitesh>>As mentioned on page 4-17 of the ADSP-214xx HRM Rev 1.0, with PKDIS=0, the address 0x200000 maps to the physical address 0x800000 (left shifted by 2bits). For more details, please refer the HRM.

I will very apperciate your fast respond since this issue is critical to me.

Best regards

Dotan

Thanks,

Mitesh

Hello Mithesh,

I have connected a 16MByte flash to 21489 (In byte mode, to MS1, and obviously have used all 24 address lines).

Please let me know if below mentioned statements are correct/incorrect.

• With packing disabled (i.e. PKDIS=1), i will be able to access only lower 8MBytes of memory(i.e memory range from 0x4000000 to 0x47FFFFF) and it is not possible to access memory beyond 0x4800000.
• However, if packing is enabled (i.e. PKDIS=0), then i can access full 16MBytes using logical addresses from 0x4000000 to 0x43FFFFF.

Please let me know the answer at the earliest.

Regards,

Ajith

Hello Mithesh,

I got the reply for this from harshit. I also tested it in my board. Accordingly my first statement is wrong and i am able to access full 16MBytes with packing disabled.

Regards,

Ajith

H Ajith,

Thanks for letting me know. Please let me know in case you have further questions.

Thanks,

Mitesh