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Free-run timer and time-stamps on the ADSP-21469

Hi All,

I'm trying to implement a free-tun timer to deliver time-stamps on an ADSP-21469.

First of all, I cannot use the internal "core timer" because it's already in use by the VDK. I also cannot use the VDK Ticks because in my system it's set to 0.1ms and I need a much bigger accuracy. I also don't want to change the Ticks period to not have too frequent re-scheduling and other VDK related stuff.

So, what I thought was to use a Peripheral Timer in PWM single-pulse generation and query for the counter to get the time-stamps. However, there're two problem with this approach:

1- it's not a free-run timer, but I could live with that by setting it to the maximum duration and handling it. Although I'd prefer to have a true free-run timer if possible.

2- the biggest problem with this approach is that I cannot read the timer counter to get the time-stamps. As stated in the ADSP-214xx SHARC Processor Hardware Reference (rev. 1.0 from Feb 2012), page, 17-4, in the "Counter Register (TMxCNT)" description, I quote: "The counter should only be read when the respective timer is disabled. This prevents erroneous data from being returned.". The problem is, if I disable the timer to read the counter, when re-enabling it, it starts to count from the beginning again and I loose my time reference.

One more information, I don't want to have frequent interrupts on my system, so I cannot use the timer as a time base and implement the counter in SW. My goal is to have it all implemented in HW, using the already existing Peripheral Timer on the DSP.

Any help is much appreciated,

Danilo

  • Hi Danilo,

    Regarding “The problem is, if I disable the timer to read the counter, when re-enabling it, it starts to count from the beginning again and I loose my time reference.”

    >>In order to read the correct TMxCNT value, it is recommended to disable the respective peripheral timer before reading the TMxCNT value as mentioned in the ADSP-214xx Hardware Reference Manual.

    However without disabling the peripheral timer, if the TMxCNT register is read, it would represent around 7 to 8 core clock cycles lesser value than the actual TMxCNT value at that instant (i.e. the counter would have advanced by this many core clock cycles), as mentioned in the ADSP 214xx Program Reference Manual, that read latency of IOP peripheral register is 7-8 core clock cycles.

    So by taking care of the above cycle latency, I hope that the issue could be resolved accordingly.

    Kindly let me know if you have any further concerns.

    Thanks,

    Harshit