I'm facing a weird problem with a sport on ADSP-21161.
The sport is used to drive a AD5312 DAC: I configure it for data transmit, internally generated clk and fs, late frame sync, active low.
I've always used it in data dependent mode (DITFS bit low) and it worked fine.
Anyway, in a new design, I need to use the same hw configuration in data independent mode, so I programmed DIV register according to the desired clk and fs frequency and raised the DITFS bit; everything else the same. But in this configuration the sport exhibits a strange behaviour: when I write the first data to TX register, FS goes low and then it stays low. Moreover, when I write it again, I get high pulses of random length on FS !!!
If I reprogram sport for early FS, it works perfectly: I can see the periodic FS as programmed in DIV register. But this timing doesn't comply with my DAC requirements, so I need to make it work with late FS.
I browsed 21161 silicon anomaly list but I could find nothing related to this.
I'm using sport2; data transmitted on channel B (I also tried with channel A, but it is the same)
DIV2 = 0x00310004; tested many other CLKDIV/FSDIV values: always the same.
The problem seems to be related to transmit underflow: if I keep on loading TX2B with new data (i.e. with a DMA), FS behaves correctly.
Thank you in advance for any help