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ADSP-21161 SPORT behaviour with late frame sync

Hi everyone,

I'm facing a weird problem with a sport on ADSP-21161.

The sport is used to drive a AD5312 DAC: I configure it for data transmit,  internally generated clk and fs, late frame sync, active low.

I've always used it in data dependent mode (DITFS bit low) and it worked fine.

Anyway, in a new design, I need to use the same hw configuration in data independent mode, so I programmed DIV register according to the desired clk and fs frequency and raised the DITFS bit; everything else the same. But in this configuration the sport exhibits a strange behaviour: when I write the first data to TX register, FS goes low and then it stays low.  Moreover, when I write it again, I get high pulses of random length on FS !!!

If I reprogram sport for early FS, it works perfectly: I can see the periodic FS as programmed in DIV register. But this timing doesn't comply with my DAC requirements, so I need to make it work with late FS.

Why this?

I browsed 21161 silicon anomaly list but I could find nothing related to this.

I'm using sport2; data transmitted on channel B (I also tried with channel A, but it is the same)

DIV2 = 0x00310004;  tested many other CLKDIV/FSDIV values: always the same.

The problem seems to be related to transmit underflow: if I keep on loading TX2B with new data (i.e. with a DMA), FS behaves correctly.

Thank you in advance for any help

  • Hi,

    Could you please post the simplest VDSP++ project  and if possible few oscilloscope screenshots as well which shows the problem?



  • Hi,

    Since I haven't heard back from you on this, just wanted to check if you still need any assistance on this issue or we can consider it closed ?



  • Sorry for not answering immediately, but I have been out of office for last 3 days.

    The issue is still there, although in my design I bypassed it using the dma workaround (i.e. I start an infinite chained dma from an internal memory variable to sport tx register and then I write data on the variable instead of tx reg; waste of resources, but actually I made the design work).

    Here is some of the information you required:

    Previous (working) sport2 configuration

    SPCTL2 = 0x030364f0

    In this configuration FS is normally high. Whenever TX2B is written, data is correctly transmitted and FS goes low for 16 clock periods; then it stays high.

    TX2B is written only when requested, usually a few times per second, at random intervals.

    Required (not working) configuration:

    SPCTL2 = 0x0303E4f0

    Here FS is initially high, it goes low when the first data word is transmitted and then IT STAYS LOW.  When I write TX2B I can see TFS going high for a random time (one to a few sclk), then it goes low and data is transmitted.

    Note: in this configuration DERR_B bit in SPCTL2 is always raised.

    In both cases DIV2  =  4 + (20<<16)   (sclk=10MHz,TFS every 20 sclk)

    but with other sclk/tfs is the same

    I think the logic of sport behaviour is this:

    When data independent mode is activated, the FS is correctly generated only if TX2B is continuously loaded with new data (the way  I do with the dma trick). If TX2B underflows, sport signals this condition with the DERR_B bit and DOESN'T raise the FS signal until a new data is ready.  Moreover I guess the random high pulse depends from the time when TX2B is loaded with new data relative to the FS period: FS is raised immediately when TX2B is asynchronously loaded but trasmission starts only at the next FS cycle.

    Last, but not least, I remark that this issue is present only with late FS. With early FS sport behaves correctly both in data dependent and data independent mode.

  • Hi,

    Thanks for the details. I do understand the issue better now. At this point, I am not really sure why the FS signal behaves the way you described. We shall definitely try to debug this and find out whether the behavior is expected. For that, can I request you to send me a couple of oscilloscope screenshots along with a simplest VDSP++ code which shows the problem?

    Having said that, I think before that, I would like to understand more about your exact requirements from the DSP-DAC interface in your system. Based on that, we can first try to find out which SPORT configuration would be the best suited for the same. So, could you please elaborate more on your exact requirements in terms of the SPORT signals end and why do you think that using data independent and late frame sync is the only option you have to meet them?



  • This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin