Unstable JTAG connection to custom board with ADSP-21489

Hi,

Could you tell me is your JTAG is passing through the Visual DSP ++ Configurator tool to run the JTAG test?

Just in order to make sure that there is nothing wrong with the USB-ICE, can you connect it to some other evaluation board, if you have and check if you still face the JTAG connection issues or not?

Could you probe whether the RESETOUT signal is getting triggered or not as well?

Apart from this, I request you to kindly go through the EE-68 and EE-175, Application Notes, which should help you in troubleshooting the Emulator and Evaluation hardware issue. The link for these notes are given below:

1. http://www.analog.com/static/imported-files/application_notes/ee-68_rev10.pdf
2. http://www.analog.com/static/imported-files/application_notes/EE175v13.pdf

Kindly go through above links and let me know in case you have any further queries/doubts.

Thanks,

Harshit

It passes the JTAG test with continuous scan. I have connected the USB-ICE to the ADSP-21489 EZ-Lite board and verified that the emulator is working properly. I can't probe the RESETOUT signal easily since there is conformal coating on the DSP chip on the board.

I realise that the BOOT_CFGx pins on this custom board are left floating (i.e. not connected). Do we have to connect themn to a specific logic level even if we do not intend to boot via SPI?

Hi,

As mentioned in the ADSP-21489 datasheet, on page 16/68 , the BOOT_CFG pin must be valid before RESET line is asserted. So these pins cannot be left floating. If you do not want it to boot via SPI, and directly execute it from the internal ROM after reset then you can set the BOOT_CFG pin to 11 as mentioned in the datasheet.

The link for the datasheet is given below:

http://www.analog.com/static/imported-files/data_sheets/ADSP-21483_21486_21487_21488_21489.pdf

Please let me know in case you have any further queries/doubts.

Thanks,

Harshit

I have double-checked and the board has the BOOT_CFGx pins wired for SPI master. I am not sure what else I need to check. This issue with the custom board occurs on and off, sometimes we can always halt and reset the processor before a debug run with a .dxe file, sometimes it just refuses to halt. It happens more frequently if a .ldr is loaded into the flash chip connected via SPI. Any suggestions to help with the troubleshooting will be great.

Hi,

I would recommend contacting private support, so that our hardware team can get a copy of your schematics and review them. If you wish to do this, please use the link below, and include a link to this thread:

http://www.analog.com/support

Regards,

Craig.

Hi, the issue has been resolved. The issue was with the custom cable that was used to interface the custom board and the USB-ICE. Adding a 33ohm resistor on the TDO line also helped to ensure that we can always halt the processor to load a new executable during debug runs.