Interrupt period jitter with ADSP21469

Question

Hi 
 I hope anyone of you can help me on this point. 
 I'm using a cyclic interrupt with the ADSP21469 and I monitor the isr period and duration with a processor output flag. 
 The interrupt period is 20us and it can be generated by the dsp timer or by a fpga connected to irq1. 
 Both case the behaviour is the same and I see a jitter of about 1.1us on isr start. 
 In particular, I see some isr calls are delayed of this quantity, while the next one is correct (namely, the average period is correct, 20us) 
 The anomaly gets worse if I execute the normal code in my application, while it almost disappears if I place a while(1) idle loop in the main function. 
 The behaviour is the same with normal interrupt or with fast interrupt (use of secondary registers, register isr with interruptf() functions) 
 I have the same code running on a ADSP21161 and I don't have this problem.

cristiano · Accepted Answer

Hi all 
 For all who care, I have some useful information about this topic. 
 More than two years after my original post I had again to face this problem. At that time the 1us jitter was not really an issue, so I didn't bother about it and I didn't want to lose more time on it. 
 This time, I had new design requirements and I really needed to get rid of it. So I spent some time in analyzing it and I eventually could find the reason and the simple solution. 
 Actually there is a bug in the code samples provided by AD. 
 In the DDR2 initialization code of some samples (i.e. Power on self test for 21469 EZKit) I have: 
 #define DDR2TRFC (0x20 << 26 ) 
 but the 26 shift is incorrect, since the DDR2TRFC field is located at bit offset 21 in DDR2RRC register. 
 I replace the define with 
 #define DDR2TRFC (0x20 << 21 ) 
 and the jitter was reduced to the 100ns level.)