Debugging SPI slave boot on ADSP-2126x

Hi,

after successfully developing and testing an application on an ADSP-21262 with SPI slave boot from an ATMega644  i redesigned the board and got stuck when booting. The (as i hope) only change was switching the compiled code from ADSP-21262 to ADSP-21261. The 21261-code works fine on the old hardware with the ADSP-21262.

To overcome this problem i have the following question:

Is it true that the RESETOUT only goes high after a reset when the processors has a sane clock and the 4096 CLKIN cycles have finished? Is this a valid indication for a working processor core?

Regards, Kurt

  • Hi Kurt,

    Regarding “Is it true that the RESETOUT only goes high after a reset when the processors has a sane clock and the 4096 CLKIN cycles have finished? Is this a valid indication for a working processor core?”

    >>That’s true. PLL requires some time to achieve phase lock . After the external processor RESET signal goes from low to high, the PLL starts operating. The rest of the chip will be held in reset for 4096 CLKIN cycles after RESET is deasserted. This sequence allows the PLL to lock and stabilize. When the RESETOUT goes High after 4096 cycles  , the rest of the chip goes out of RESET and then the booting process starts.

    Thanks,

    Mahesh