Post Go back to editing

ADSP21469 Timer0 PWM Mode Jitter

Hi,

I am using the code below to set up timer0 to create a PWM output with a fixed period and from time to time I change the width.

   

*pTM0CTL = 0;                                                             // Clear any old settings

*pTM0CTL = (TIMODEPWM | PULSE | PRDCNT );          // Set PWM mode, High output, Count to end of period

*pTM0CNT =    0x01;

*pTM0PRD =     PWM_Freq;                                         // Set to 40kHz

*pTM0W =     PWM_VCXO;                                          // Set default to 50% Duty

asm("NOP;");

asm("NOP;");

*pTM0STAT = (TIM0EN);

There are no interrupts enabled for timer0 and it simply auto reloads at the end of each period count.

When no other interrupts are enabled I get a very nice PWM output and can vary the width from 0-100% with no measurable jitter.

When other interrupts are enabled I'm getting up to 1us jitter on the period.

I'm creating approximately 40kHz PWM so 1us represents a large % of the period.

Since this is a free-running hardware timer with no interrupts required to reload it why is there  jitter when other interrupts are enabled.

I can understand interrupt latency causing jitter if software had to handle the interrupts for timer0 but there is none for this timer and it's supposed to be hardware based...

Is there some latency in the hardware reload that is interrupt dependant?

Is there another way to configure the timer to produce PWM jitter-free (well, low jitter within the spec of the device)?

I can't use the PWM outputs because this chip does have them or the ability to map to the DPI...

Thanks in advance.

  • Hi Warren,

    Can you please provide a simple code which replicates the issue on the ADSP-21469 EZ-Kit lite.

    We will look into the code and try to find the root cause of the issue.

    Also kindly upload your scope captures in order to enable us understand the issue more clearly.

    Thanks,

    Harshit

  • Hi Harshit,

    I've found a workaround for this problem.

    I'm using the PCG to generate PWM which it does nicely without any jitter.

    I never found out exactly why there was jitter on the Timer0 PWM output. If I set the system up so only Timer0 was running with no interrupts active there was no jitter. Once some interrupts were enable there was a small amount of jitter which increased as more interrupts were re-enabled. When all the Sport interrupts and Timer1 interrupts were enabled + all the FIR filters running the jitter on the PWM output pin was as high as 1us on a PWM period of 25uS so 4%. It was actually period jitter - the pulse width was always very accurate but the total 25us period could extend to 26us. It was as if the core had to reload the period count into Timer0 when it timed out - is this how it works?

  • Hi Warren,

    Glad to know that you have got the work-around for your problem.

    But as far as Peripheral timer is concerned, once it is timed out , it automatically reloads the period count. A timer interrupt is generated at the end of each period. An ISR must clear the interrupt latch bit TIMxIRQ and might alter period and/or width values. So I would suggest you to try replicating the issue with simple code and send it to us, so that we can look into it and try to find the root cause of the jitter.

    Thanks,

    Harshit

  • Hi Again,

    I wish to advise I have dumped the AD DSP from my design. I could not get it to perform with low jitter without design compromise. I'm now using a FPGA + i5-4250u in an Intel NUC and have none of the design compromise issues I had with this DSP + significantly more horsepower. Thanks for all your help however.

  • This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin