Problems with ADSP21262 JTAG interface and Building

Hi,

I can think of the below suggestions which should help you to resolve the connection issues provided the schematics are all same and in accordance to the ADSP-21262 EZ-Kit lite:

1. Make sure that the power-up sequence requirements needed for the processor is taken care as per the datasheet.

http://www.analog.com/static/imported-files/data_sheets/ADSP-21261_21262_21266.pdf

2. Can you change the CLK_CFG1-0 to 01 instead of 10 and check if it resolves the issue at your end?

3. Are you initializing the PLL in your application? Make sure that the PLL is configured for the correct frequency. I have seen this error message when the PLL is not configured properly.

Thanks,

Harshit

Hi,

Thanks a lot for your suggestions!

I still have some quenstions about your suggestions.

1, For ADSP-21262SBBC-150, CLKIN frequency is from 6.25MHz to 50MHz while CCLK frequency is from 100MHz to 150MHz as referenning to the Table 16 in the datasheet

http://www.analog.com/static/imported-files/data_sheets/ADSP-21261_21262_21266.pdf

Why should I change the CLK_CFG1-0 to 01(16:1) instead of 10(8:1) for CLKIN=10MHz or 13.3MHz?

2, I had initialized the PLL correctly in my project, but it's just only connecting or building the project ,not running the project, while meeting with all the errors I have mentioned.

Thans for your more suggestions.

Hi,

As I can see in the datasheet on Table 16 of the datasheet  , it shows that the CLK period of 160ns (i.e. 6.25MHz) is valid only for condition where CLK_CFG= 01.

So I understand that for lower CLKIN values it is good to have CLK_CFG of 01, as it means that when the processor comes out of reset then the CCLK:CLKIN ratio of 16:1 will bring the CCLK to be in the range of 100MHz to 150MHz.

Considering your case for a CLKIN of 10 and CLK_CFG = 10 (8:1), the CCLK will be 80MHz , which is less than what is specified in the datasheet.

So you need to take care that when processor comes out of power on reset, the CLK_CFG pins makes the CCLK to be somewhere in the range supported as mentioned in the datasheet, otherwise unpredictable behavior will be observed on processor.

Also if you are initializing PLL inside the code, make sure that the CCLK range is in accordance with the datasheet.

The link for the datasheet is given below:

http://www.analog.com/static/imported-files/data_sheets/ADSP-21261_21262_21266.pdf

Hope this helps.

Please let me know in case you have any further queries/doubts.

Thanks,

Harshit

Hi,

Thanks again for your help!

I used a CLKIN of 20MHz and CLK_CFG = 10 (8:1), then the target connected successfully.

Then I builded  the examples in ...\Analog Devices\VisualDSP 5.0\212xx\examples\ADSP-21262 EZ-KIT Lite, there was the error:

Failed to set automatic breakpoint at ‘main’!

My board use  ADSP-21262SBBC-150, while the ADSP-21262 EZ-KIT Lite use ADSP-21262SKBC-200. I could't find any diferences between them about memory according to the datasheet ADSP-21261_21262_21266.pdf.

When I builded my project, there was still the ‘main’ error.

Why does this happen?

Thanks,

Sophie Zhang

Hi,

Thanks again for your help!

I used a CLKIN of 20MHz and CLK_CFG = 10 (8:1), then the target connected successfully.

Then I builded  the examples in ...\Analog Devices\VisualDSP 5.0\212xx\examples\ADSP-21262 EZ-KIT Lite, there was the error:

Failed to set automatic breakpoint at ‘main’!

My board use  ADSP-21262SBBC-150, while the ADSP-21262 EZ-KIT Lite use ADSP-21262SKBC-200. I could't find any diferences between them about memory according to the datasheet ADSP-21261_21262_21266.pdf.

When I builded my project, there was still the ‘main’ error.

Why does this happen?

Thanks,

Sophie Zhang

Hi Sophie,

Sorry for the delay in response.

As mentioned above can you check if the power up sequence is as per datasheet or not.

I would request you to kindly probe the VDDint, VDDext, CLKIN and RESET signal and check if there is any deviation from the specification as  mentioned in the datasheet.

Thanks,

Harshit

thank you for your reponse!

I have found the problem with RESET. Nearly the same with other problem, I set the pins into wanted state by FPGA, then it's OK!