How to generate interrupt using external clock and frame sync?

DSP: 21489

Audio Codec:AD73322L

Operation mode: Using AD73322L generate bit clock,frame sync.

Question: The DMA is work,but no interrupt generate.When using Internal clock the DMA interrupt enter. Why & How to do?

Thanks.

Init code:

section("seg_dmda") unsigned short RxBlock_A0[64];

section("seg_dmda") unsigned short RxBlock_A1[sizeof(RxBlock_A0)];

  //Set up the TCBs to rotate automatically

int TCB_RxBlock_A0[4] = { 0, sizeof(RxBlock_A0), 1, 0};

int TCB_RxBlock_A1[4] = { 0, sizeof(RxBlock_A0), 1, 0};

   *pSPCTL1 |= (SLEN16 | FSR | DIFS | CKRE | LFS | SDEN_A | SCHEN_A);

    TCB_RxBlock_A0[0] = (unsigned int) TCB_RxBlock_A1 + 3 - OFFSET + PCI ;

    TCB_RxBlock_A0[3] = (int) RxBlock_A0 - OFFSET ;

    TCB_RxBlock_A1[0] = (unsigned int) TCB_RxBlock_A0 + 3 - OFFSET + PCI ;

    TCB_RxBlock_A1[3] = (int) RxBlock_A1 - OFFSET ;

   *pCPSP1A = (unsigned int)TCB_RxBlock_A0 - OFFSET + 3;  

   *pSPCTL1 |= ( SPEN_A);

  • 0
    •  Analog Employees 
    on Mar 18, 2014 6:32 AM over 6 years ago

    Hi Liu,

    I have attached a VDSP project file (SPORT_Standard_Serial with PCG as CLOCK source.zip) for your reference. Please find the attached code which can be directly run on the ADSP-21489 EZ-kit. In the code the SPORT uses the standard DMA for the transferring the data. The SPORT0 is configured as ‘Transmitter’ and SPORT1 is configured as ‘Receiver’. Both the SPORTs are configured to use the externally-generated Clock and Frame Sync which is generated by PCG_A. After running the code you can observe that the DMA interrupt is occurred in both cases, where the completion of SPORT0 DMA transfer and the completion of SPORT1 DMA reception.

    Please let me know if you have further queries/doubts.

    Regards,

    Jithul

    SPORT_Standard_SerialwithPCGasCLOCKsource.zip