Questions about Programming Code into SPI Flash with ADSP21479

Question

Hi 
 After my code (work with ADSP21479) passed debug, I programmed the code into the SPI Flash Mem by the generated .ldr file in which I configured as followed: 
 https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/397/bfc1bae0d746c87afc9c362d38a34b2f.html 
 After I programmed the code and tested the DSP boards, I got some questions as followed: 
 1. I used ADZS-USB-ICE/VisualDSP++ or a 3rd Party Programmer(JTAG port) to program the same Loader file generated by VisualDSP, but only part of the programmed DSPs work, say, about 50%. 
 2. When I ran the failed DSP under ADZS-USB-ICE and VisualDSP, and when build a project, it always ran by itself but not ran the code part. And some times I got following information: 
 https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/397/3010.bfc1bae0d746c87afc9c362d38a34b2f.html 
 3. I found the good programmed DSP always work well, but the bad ones could work very few times during multiple running (Power On and DSP Reset). I checked one of the bad DSP board with a simple testing code that just generates pulses at Flag0; it worked only two times when I ran it for tens of times. Followed pictures show the same DSP board at the cases of work and not work after the DSP Reset: 
 (In the diagrams: the Yellow trace is DSP Reset, the Blue one is SPI Flash Data-out, the Purple one is SPI Clock, and the Green one is the Flag0 output.) 
 https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/397/4137.bfc1bae0d746c87afc9c362d38a34b2f.html 
 Work case after the DSP Reset 
 https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/397/5100.bfc1bae0d746c87afc9c362d38a34b2f.html 
 No work case after the DSP Reset. 
 4. When I built the Loader file, if I choose Release for the Settings for Configuration, the programmed DSP running got different result with ones under the emulator(ADSZ-USB-ICE)/VisualDSP. 
 Would you please check my questions and the attached files to findout the possible reasons that make the issue? 
 (I am not sure if you could see the pictures when I post, I also attached the posted pictures). 
 Please let me know should you need other information about my questions. 
 Thank you, 
 Ning

ADIApproved · Accepted Answer

Hi Ning , 
 To bypass the P LL and SDRAM initiation insid e the Kernel file (479_spi.asm), you have to only comment the “#define EXT_MEMORY” line in the ‘479_spi.asm’. Please find the attached modified Kernel file (479_spi.asm) for your reference. 
 While looking at your attached " 479_spi_Bypass.asm.zip " file, I feel that you are confused with the word i mentioned before, "bypassing PLL initialization". what I exactly meant by this is 'avoid the PLL & SDRAM initialization fully in the Kernel file'. I can see that you have simply placed the PLL in 'bypass mode' in your code , and this is not correct. However, instead of doing this if you can configure the correct PLL initialization according to your system CLKIN and desired CCLK frequency ( modify the values of ‘PLLM, PLLD, INDIV’ bits in the PMCTL register ) in the kernel file, it should be fine. 
 Please let me know how you get on. 
 Thanks, 
 Jithul)

ADIApproved · Answer

Hi Ning , 
 I understand that you are facing some booting issue in the ADSP-21479 processor. In order to assist you better with this issue please provided the details given below. 
 
 Can you please clarify that you are using EZ-Kit or custom board? 
 You mentioned, “When I ran the failed DSP under ADZS-USB-ICE and VisualDSP, and when build a project, it always ran by itself but not ran the code part. And sometimes I got following information:”. I can see that you have embedded an image here, but unfortunately I can’t able to view it. Can you please attach the image again? 
 I can see in your “Loader Config1.png” that you are not using the default kernal while generating the ‘Loader(.ldr)’ file. Can you please provide the details about the modified Kernal file that you have used? 
 Can you please try booting the processor using the Loder file which generated in ‘debug’ active configuration mode (In ‘Release’ mode VDSP builds a project with optimization enabled.) 
 
 If you are using custom board, so in order to investigate this issue can you please do the following debugging steps. 
 
 Boot Configuration Select pins (BOOT_CFG2–0) select the boot mode for the processor. The BOOT_CFG pins must be valid before RESET (hardware and software) is de-asserted. Please check the custom board to make sure that the boot configuration pins are set properly for SPI master booting. The Boot Mode Selection table is given below. 
 Ensure that the /TRST signal of the JTAG ICE is connected to board ground. Do not leave this signal floating. Letting this signal float may cause boot failures or other memory access failures. 
 Ensure that you have selected the correct parameters while generating the .LDR file. Selecting an inappropriate parameter may cause the boot to fail. Ensure that the correct boot kernel is used before generating the loader (.LDR) file. If you are using a modified boot kernel, try using the default boot kernel supplied with VisualDSP++ together with an example application (like flag toggle) to confirm basic boot-loading. 
 Verify the Power-Up Sequencing timing diagram which is mentioned in the ADSP-21479 datasheet. And make sure that is the processor is properly coming out of RESET. 
 Make sure that the PLL is configured correctly. The default boot kernel may have the PLL configuration as per the EZ-KIT Lite board. This need to be changed if your application uses a different CLKIN. Check the CLKCFG signals and ensure that the PLL is not overdriven. Ensure that the ratio selected in combination with the CLKIN frequency does not exceed the core clock to a value greater than specified. 
 
 Thanks & Regards Jithul

ADIApproved · Answer

Hi Ning , 
 Thanks for further details. Please find my answers given below 
 1) I generated the Loader file according the configurations listed in the attached file, these configuration are correct? Especially I didn't use the default Kernel but the 479_spi.dxe currently, is it correct?(Besides, sometimes I selected Debug and sometimes Release, what is the difference between the both? and what is the difference between the format Hex and Binary?) 
 >> The information given in the attached document ‘Configurations for building Loader file for ADSP21479.docx’ looks fine. But I can see an obvious mistake in the first image, where the Target Type option selected as “Executable file”. For generating the loader file the type should be selected as “Loader file”. 
 I can see in your test code that you have used the CLKIN of 25MHz and configured the PLL to generate the CCLK of 150MHz (where the PLLM value is 6). But in the EZ-Kit, the CLKIN is used as 16.625MHz. In the default Boot Kernel(479_spi.dxe) the PLL is configured to generate the CCLK value of 266MHz using the PLLM value of 16. So if you are using the default boot kernel in your custom design the PLL will be over-driven. Thus you need to modify the boot kernel according to your CLKIN. 
 Also, can you please provide the information about Core to CLKIN Ratio (CLK_CFG1–0) configured. Check the CLKCFG signals and ensure that the ratio selected in combination with the CLKIN frequency does not exceed the core clock to a value greater than specified. 
 The difference between binary and Intel hex loader file is already discussed in another thread in the forum, please look into the thread given below. 
 https://ez.analog.com/message/8083#8083 
 The difference between Debug and release mode are discussed in the flowing thread, please have a look at it. 
 https://ez.analog.com/message/9170#9170 
 2) I read some article that said the length of the JTAG was limited. In my test fixture, the JTAG cable from your ADZS-USB-ICE is about 11 inches (seems shielded), and our one is about 10 inches (not shielded); is the JTAG connection is too long to affect the programming? If it is, what is the ideal length of our JTAG cable. Would you please give me suggestion to the JTAG connection with the ADZS-USB-ICE? 
 >> As far as my understanding is concerned, you have to b uffer your target if the worst-case route distance between the "JTAG emulator header and the DSP" is greater than six (6) inches, regardless of the number of DSPs in the scan chain path. But I am not well aware of the restriction in lenght of the JTAG cable. W e have an application note (EE-68) which provides technical information to properly design a JTAG emulator interface for Analog Devices digital signal processors (DSPs) targets. You can download the application note via the link given below. 
 https://www.analog.com/static/imported-files/application_notes/ee-68.pdf 
 3) In another attachment, there are the diagrams that list the timings of our current Power On DSP-Reset, SPI Clk, SPI Flash Data_out and the pulses generated by Flag0 when the checking code could be run. The three pictures showed the same DSP board at multiple power on tests. My question is the current Power On DSP-Reset would affect the DSP booting? (I also plan to do some check for this.) 
 >> Improper Power-Up Sequencing could affect the booting of the processor. Here I have attached the Power-Up Sequencing timing diagram for ADSP-21479 processor (same is given in the page no 26 / 76 of the datasheet). Can you please provide the screenshots of Power-Up Sequencing (/RESET, VDDINT, VDDEXT, CLOCKIN, CLK_CFG1-0 and /RESETOUT) of your custom board. Please make sure that the power-up sequence requirements needed for the processor is taken care as per the attachment. 
 4) The third attachment lists the information from Visual DSP++, when I applied the bad programmed DSP board with it. What do these information mean? 
 >> Can you please confirm these errors are only happening for ‘bad programmed DSP board’. I have seen the error [Failed to set automatic breakpoint at "main"] in past when the PLL is programmed with PLLM and N values accidently which produce the CCLK more than what is supported by the processor. Make sure that the power-up sequencing is proper and the processor is properly coming out of RESET. 
 Thanks & Regards 
 Jithul

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Questions about Programming Code into SPI Flash with ADSP21479