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Questions about Programming Code into SPI Flash with ADSP21479

Hi

After my code (work with ADSP21479) passed debug, I programmed the code into the SPI Flash Mem by the generated .ldr file in which I configured as followed:

https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/397/bfc1bae0d746c87afc9c362d38a34b2f.html

After I programmed the code and tested the DSP boards, I got some questions as followed:

1. I used ADZS-USB-ICE/VisualDSP++ or a 3rd Party Programmer(JTAG port) to program the same Loader file generated by VisualDSP, but only part of the programmed DSPs work, say, about 50%.

2. When I ran the failed DSP under ADZS-USB-ICE and VisualDSP, and when build a project, it always ran by itself but not ran the code part. And some times I got following information:

https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/397/3010.bfc1bae0d746c87afc9c362d38a34b2f.html

3. I found the good programmed DSP always work well, but the bad ones could work very few times during multiple running (Power On and DSP Reset). I checked one of the bad DSP board with a simple testing code that just generates pulses at Flag0; it worked only two times when I ran it for tens of times. Followed pictures show the same DSP board at the cases of work and not work after the DSP Reset:

(In the diagrams: the Yellow trace is DSP Reset, the Blue one is SPI Flash Data-out, the Purple one is SPI Clock, and the Green one is the Flag0 output.)

https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/397/4137.bfc1bae0d746c87afc9c362d38a34b2f.html

Work case after the DSP Reset

https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/397/5100.bfc1bae0d746c87afc9c362d38a34b2f.html

No work case after the DSP Reset.

4. When I built the Loader file, if I choose Release for the Settings for Configuration, the programmed DSP running got different result with ones under the emulator(ADSZ-USB-ICE)/VisualDSP.

Would you please check my questions and the attached files to findout the possible reasons that make the issue?

(I am not sure if you could see the pictures when I post, I also attached the posted pictures).

Please let me know should you need other information about my questions.

Thank you,

Ning

attachments.zip
Parents
  • Hi Jithul,

    Thank you so much for giving the detailed explanation for my question. I just checked the hardware configuration of the DSP board and my test fixture. Now I list the checking result and the questions with them according to the order of your explanations:

    1. In my Loader configuration I selected "Loader File" (that wrong picture in the file was form other place I didn't check, sorry about it.). For the CLK_CFG1–0, we set as 00, so the Core to CLKIN Ratio should be 8:1; in this situation, do I need to modified the Kernel file (479_spi)? If I need, would you please give me some guide do that? (I found the 479_spi.asm, but I haven't reached the assembly language of the ADSP so far.)


    2. I am reading the EE Note 68. Because I don't use any buffer for the JTAG connection path in my TF, and our JTAG cable to the Emulator JTAG header is about 10 inches, I'd better to shorten it less than six inches. Do you think it's necessary?


    3. I tested the timing of VDDEXT, VDDINT, DSP_Reset and CLKIN and paste them in the attached file (I couldn't get /RESETOUT, because there is no lead to the the pin on our DSP board.) On our DSP board, the real DSP_Reset is delayed about 300 mS after power on, and according the datasheet, the tCLKRST and tPLLRST should be zero, that may affect the boot processing, but I don't know what happens when the real DSP_Reset comes. Any idea about it? Besides, I want to see what happens if the DSP_Reset starts at Power On. In fact, we have a RC circuit for the reset at power on, the fourth picture on the attached files shows the timing of the both; you can see the reset is pretty slope (not good raising edge); my question is: do I need  something like Schmitt-trigger Inverter to improve the signal?


    4. I have used the VisualDSP++ and Emulator (ADZS-USB-ICE) for about two years. The VisualDSP info with the bad programmed board (showed in the attachment I posted last time) could be just seen recently (if my memory is ok) when I checked the DSP programming. In fact, most frequently, the VisualDSP just not build the project properly when add the bad programmed board on my TF. When I build a project with the board (even for Executable File), it always starts by itself but not performs the built code as the picture I put in another attached file. Any comment for this phenomenon? Or you need more information about it?

    Should you need any other information or files, please let me know.

    Thanks again,

    Ning


    attachments.zip
Reply
  • Hi Jithul,

    Thank you so much for giving the detailed explanation for my question. I just checked the hardware configuration of the DSP board and my test fixture. Now I list the checking result and the questions with them according to the order of your explanations:

    1. In my Loader configuration I selected "Loader File" (that wrong picture in the file was form other place I didn't check, sorry about it.). For the CLK_CFG1–0, we set as 00, so the Core to CLKIN Ratio should be 8:1; in this situation, do I need to modified the Kernel file (479_spi)? If I need, would you please give me some guide do that? (I found the 479_spi.asm, but I haven't reached the assembly language of the ADSP so far.)


    2. I am reading the EE Note 68. Because I don't use any buffer for the JTAG connection path in my TF, and our JTAG cable to the Emulator JTAG header is about 10 inches, I'd better to shorten it less than six inches. Do you think it's necessary?


    3. I tested the timing of VDDEXT, VDDINT, DSP_Reset and CLKIN and paste them in the attached file (I couldn't get /RESETOUT, because there is no lead to the the pin on our DSP board.) On our DSP board, the real DSP_Reset is delayed about 300 mS after power on, and according the datasheet, the tCLKRST and tPLLRST should be zero, that may affect the boot processing, but I don't know what happens when the real DSP_Reset comes. Any idea about it? Besides, I want to see what happens if the DSP_Reset starts at Power On. In fact, we have a RC circuit for the reset at power on, the fourth picture on the attached files shows the timing of the both; you can see the reset is pretty slope (not good raising edge); my question is: do I need  something like Schmitt-trigger Inverter to improve the signal?


    4. I have used the VisualDSP++ and Emulator (ADZS-USB-ICE) for about two years. The VisualDSP info with the bad programmed board (showed in the attachment I posted last time) could be just seen recently (if my memory is ok) when I checked the DSP programming. In fact, most frequently, the VisualDSP just not build the project properly when add the bad programmed board on my TF. When I build a project with the board (even for Executable File), it always starts by itself but not performs the built code as the picture I put in another attached file. Any comment for this phenomenon? Or you need more information about it?

    Should you need any other information or files, please let me know.

    Thanks again,

    Ning


    attachments.zip
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