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Questions about Programming Code into SPI Flash with ADSP21479

Hi

After my code (work with ADSP21479) passed debug, I programmed the code into the SPI Flash Mem by the generated .ldr file in which I configured as followed:

https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/397/bfc1bae0d746c87afc9c362d38a34b2f.html

After I programmed the code and tested the DSP boards, I got some questions as followed:

1. I used ADZS-USB-ICE/VisualDSP++ or a 3rd Party Programmer(JTAG port) to program the same Loader file generated by VisualDSP, but only part of the programmed DSPs work, say, about 50%.

2. When I ran the failed DSP under ADZS-USB-ICE and VisualDSP, and when build a project, it always ran by itself but not ran the code part. And some times I got following information:

https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/397/3010.bfc1bae0d746c87afc9c362d38a34b2f.html

3. I found the good programmed DSP always work well, but the bad ones could work very few times during multiple running (Power On and DSP Reset). I checked one of the bad DSP board with a simple testing code that just generates pulses at Flag0; it worked only two times when I ran it for tens of times. Followed pictures show the same DSP board at the cases of work and not work after the DSP Reset:

(In the diagrams: the Yellow trace is DSP Reset, the Blue one is SPI Flash Data-out, the Purple one is SPI Clock, and the Green one is the Flag0 output.)

https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/397/4137.bfc1bae0d746c87afc9c362d38a34b2f.html

Work case after the DSP Reset

https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/397/5100.bfc1bae0d746c87afc9c362d38a34b2f.html

No work case after the DSP Reset.

4. When I built the Loader file, if I choose Release for the Settings for Configuration, the programmed DSP running got different result with ones under the emulator(ADSZ-USB-ICE)/VisualDSP.

Would you please check my questions and the attached files to findout the possible reasons that make the issue?

(I am not sure if you could see the pictures when I post, I also attached the posted pictures).

Please let me know should you need other information about my questions.

Thank you,

Ning

attachments.zip
Parents
  • Hi Jithul,

    Thank you very much for answering my question about DSP code programming.(I just saw your email when I checked my question here; I wonder why I haven't received an email notice for your answer.)

    According to your points, let me introduce the context of my DSP programming. My test code is written by C (and use asm("nop") inside) and my code is run for our own DSP board (ADSP 21479) (in my last post about the questions, I attached a simple checking code just for checking if the code was programmed); we set BOOT_CFG2-0 as 001; the /TRST is grounded per a 4.7K res on the board; the Power On DSP_Reset is generated by a uC on another board, and it is different from the one in the ADSP21479 datasheet, and it doesn't match the timing of Power On Reset in the datasheet per my understanding, but it works well for our production code so far; on my Test Fixture for testing the DSP board, we add a 10-inch no shielded JTAG cable and it is connected to your JTAG cable (11-inch) from ADZS-USB-ICE.

    My questions are followed:

    1. I generated the Loader file according the configurations listed in the attached file, these configuration are correct? Especially I didn't use the default Kernel but the 479_spi.dxe currently, is it correct?(Besides, some times I selected Debug and sometimes Release, what is the difference between the both? and what is the difference between the format Hex and Binary?)

    2. I read some article that said the length of the JTAG was limited. In my test fixture, the JTAG cable from your ADZS-USB-ICE is about 11 inches (seems shielded), and our one is about 10 inches (not shielded); is the JTAG connection is too long to affect the programming? If it is, what is the ideal length of our JTAG cable. Would you please give me suggestion to the JTAG connection with the ADZS-USB-ICE?

    3. In another attachment, there are the diagrams that list the timings of our current Power On DSP-Reset, SPI Clk, SPI Flash Data_out and the pulses generated by Flag0 when the checking code could be run. The three pictures showed the same DSP board at multiple power on tests. My question is the current Power On DSP-Reset would affect the DSP booting? (I also plan to do some check for this.)

    4. The third attachment lists the information from Visual DSP++, when I applied the bad programmed DSP board with it. What do these information mean?

    Should you need any other information or files about my questions, please let me know.

    Thanks a lot for answering so many new questions in advance,

    Ning Fu


    attachments.zip
Reply
  • Hi Jithul,

    Thank you very much for answering my question about DSP code programming.(I just saw your email when I checked my question here; I wonder why I haven't received an email notice for your answer.)

    According to your points, let me introduce the context of my DSP programming. My test code is written by C (and use asm("nop") inside) and my code is run for our own DSP board (ADSP 21479) (in my last post about the questions, I attached a simple checking code just for checking if the code was programmed); we set BOOT_CFG2-0 as 001; the /TRST is grounded per a 4.7K res on the board; the Power On DSP_Reset is generated by a uC on another board, and it is different from the one in the ADSP21479 datasheet, and it doesn't match the timing of Power On Reset in the datasheet per my understanding, but it works well for our production code so far; on my Test Fixture for testing the DSP board, we add a 10-inch no shielded JTAG cable and it is connected to your JTAG cable (11-inch) from ADZS-USB-ICE.

    My questions are followed:

    1. I generated the Loader file according the configurations listed in the attached file, these configuration are correct? Especially I didn't use the default Kernel but the 479_spi.dxe currently, is it correct?(Besides, some times I selected Debug and sometimes Release, what is the difference between the both? and what is the difference between the format Hex and Binary?)

    2. I read some article that said the length of the JTAG was limited. In my test fixture, the JTAG cable from your ADZS-USB-ICE is about 11 inches (seems shielded), and our one is about 10 inches (not shielded); is the JTAG connection is too long to affect the programming? If it is, what is the ideal length of our JTAG cable. Would you please give me suggestion to the JTAG connection with the ADZS-USB-ICE?

    3. In another attachment, there are the diagrams that list the timings of our current Power On DSP-Reset, SPI Clk, SPI Flash Data_out and the pulses generated by Flag0 when the checking code could be run. The three pictures showed the same DSP board at multiple power on tests. My question is the current Power On DSP-Reset would affect the DSP booting? (I also plan to do some check for this.)

    4. The third attachment lists the information from Visual DSP++, when I applied the bad programmed DSP board with it. What do these information mean?

    Should you need any other information or files about my questions, please let me know.

    Thanks a lot for answering so many new questions in advance,

    Ning Fu


    attachments.zip
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