I'm experiencing an issue in SPORT1 DMA.
This happens randomly and mostly at high temperatures.
Once in a while I get an error that the SPORT DMA is not finished. This is SPORT1 and it is not shared.
Clock and frame are externally generated from a FPGA and debugging showed that the FPGA sent all the required frames.
Then when I printed out the internal DMA counter (*pC1) when the error happened, it showed 0. Meaning that the DMA is infact finished, but for some reason it is not reflected in the pDMASTAT register.
Anybody know any reason why this could happen?