I need some technical support for the chip ADSP-21363 rev. 0.5; I'm using VisualDSP 18.104.22.168 (January 2007) on Windows XP.
My clock setup is CLKIN = 50MHz and CCLK (CORE CLOCK) = 300MHz.
The SPORT0 is trasmitting only on channel A (channel B is actually disabled), driven by external SCLK and FSync, DATALEN = 32.
DMA is configured in chaining mode, with 67 words counting on both blocks.
The SCLK period is 80ns, then every 80ns x 32bit x 67words = 171560ns an interrupt is raised from DMA SPORT.
The interrupt handler manages an I/O that is cleared on start and set on exit, thus this signal have normally a period of 171560ns, with a small latency and with a small low duty-cycle during handler management.
The problem is that, about every 1 second, we trigger at the oscilloscope that this I/O is active two times at very small distance: the interrupt is triggered two times, but it is not possible that DMA completes the transfer in this small amount of time: this is a mistake and this problem leads to great problems with my software.
What do you think about this double-interrupt generation? Do you have any informations about this phenomenon?
Thanks in advance.