ADSP21489 interfacing with AD9248

Hi ,

One of my customer is facing a problem in reading the two channel continuous data parallely with PDAP.

The Question is.

He is using the AD9248 two channel ADC, channel-1 data on the posedge and channel-2 data on the negedge. When he is trying to process the data with PDAP, He is able to see only the channel-1 data which is obtaing on the posedge.

Could some one can help me on this how can mu customer take the two channels data with PDAP is there any mechanism.


jangi Reddy

  • 0
    •  Analog Employees 
    on Sep 3, 2014 7:46 AM


    I have moved this from the Processors and DSP community to the SHARC Processors community. Please continue the discussion here.



  • We have a board that uses an AD9248 or 9238 that does this with PDAP. I have CLK A & CLK B tied together and a MUX _SELECT line. These go into a CPLD that I need to review the logic for.

    I know it works with both channels.

    dspblok a9248 -- Analog Devices AD9248 Hi Speed ADC I/O Board - dspblok -

    I need to leave know but I can look up the logic later today. Can you describe your connections?

    Al Clark

  • I looked at the glue logic that we used for a PDAP ad9248 interface.

    It used a div/2  FF from an input clock to create ADC CLK & ADC CHAN

    The PDAP Clock was created by a Shift register chain with 7 delays from the input clock. There was a little steering logic as well. This was so we could run single channel twice as fast or dual channel since the Ad9248 is faster than the PDAP. The SHIFT register circuit was probably to compensate for the internal pipeline in the ad9248

    We also have a trigger input.

    I realize that this is a little cryptic, but I am looking at a hard copy, not a pdf.

    I don't remember all the reasoning anymore since I designed this interface many years ago. I suggest you reread all the data sheets and see if any of this makes sense.

    I'm sure I probably drew lots of little timing diagrams on a blackboard. I also remember making sure the drives to each clock had the same propagation delays. Since this is a high speed device, make sure that you have a low jitter clock.

    Al Clark

  • 0
    •  Analog Employees 
    on Sep 9, 2014 2:04 AM


    As far as my understanding is concerned, it may not be possible to interface both channels of ADC directly to the PDAP interface. Because, the IDP_PDAP_CLKEDGE bit in the IDP_PP_CTL register selects the PDAP sampling Clock Edge. Setting this bit (= 1) causes the data to latch on the falling edge (PDAP_CLK_I signal) and clearing this bit (= 0) causes data to latch on the rising edge (default). So, you can only receive the ADC data through PDAP, either on the positive edge or the negative edge of the clock.



  • You can operate both channels with PDAP. The ADC Clock & ADC Channel are 1/2 the frequency of the PDAP clock. The ADC Clock and ADC channel are identical and switch on the inactive edge of the PDAP clock.

    You are limited to about 25 - 30 MHz sampling since the samples are alternating and the PDAP can only operate at about core clock / 8. You can actually run somewhat higher than core clock / 8 since the clocks are external. 

    The DSP is OK for capturing a burst of data and then post processing. It is not going to be too useful if you are sampling at a high rate for real time processing because there will be almost no MIPs left for processing.

    We built a combined FPGA / SHARC board that was more useful for SDR applications. The FPGA could be used for downsampling and the DSP took over for baseband processing.

    Al Clark