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ADSP-21161N, RD and WR signal and waitstate under Synchronous Read/Write as Bus Master



		

			

									
						usaghi
					
							

			
				
									
											
							 		
		        	            							
			
			    	
			                    
                
				                on Nov 4, 2014 
				
			
			
		


				
		

		    		    
		    
		    	
			
Hi,

 
When using Synchronous Read/Write as Bus Master, on ADSP-21161N, signal timing can be shown at Figure.19 on datasheet(Rev.C) page.31, as follows.

 

 
Here, it shows WR and RD signals are changed triggered by CLKIN.

 
On the other hand, when defining External Bank 0 Access Mode(EB0AM) as "10", Hardware Reference Table A-20 on page 938 is describing as follows.

 
Synchronous—processor RD and WR strobes change on CLKOUT’s edge—reads use the waitstate count setting from EBxWS (minimum EBxWS=001); writes are 1-wait state.

 
CLKOUT is output slightly delayed from CLKIN, as shown in Figure 11 of the datasheet page.23.

 

 
Thus, I believe we must consider Figure 11 and  Figure 19 at the same time, for the timing of Synchronous Read/Write as Bus Mater.

 
Please correct me if I'm wrong.

 
If it is correct, I would like to ask you following question,

 
a) When defining 1 or 2 wait-state, how this wait-state value affect to RD and WR signal on the timing chart ?

 
I think WR and RD change on CLKOUT's edge, therefore as far as CLKOUT cycle is NOT changed, WR and RD cycle(means duration time from signal rising to the next rising, or from rising to falling) will not be changed, I think, but is this correct ?

 
If my thought is NOT correct, please let me know how the value of wait-state will affect to the timing chart.

 
Best Regards, 

								


				
				
		

			
						
									
									
						
						
			
			
			
			
		


					

			





	

		
	















	

	

					



			


				
	









	
    
	

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                on Nov 7, 2014 7:21 AM
            
            
					
    
	
    

		
		
    
					
    Hi,
    
 
    Could you please anyone add any comments or reply ?
    
 
    Best Regards,
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                                 Analog Employees 
                                
                            
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                on Nov 19, 2014 10:59 AM
            
            
					
    
	
    

		
		
    
					
    Hi,
    
 
    Please see my replies below:
    
 
    “Thus, I believe we must consider Figure 11 and  Figure 19 at the same time, for the timing of Synchronous Read/Write as Bus Mater.
    
 
    Please correct me if I'm wrong.”
    
 
    >> Yes, both the timings should be taken care by the user. Also please note when interfacing to synchronous external memories, CLKIN must be used to provide the clock source to the synchronous device. CLKOUT with CLKDBL tied low can be used as a clock source to peripherals only in single processor systems.
    
 
    Even the datasheet on page 31 states that ‘Use these specifications for interfacing to external memory systems that require CLKIN, relative to timing or for accessing a slave ADSP-21161N (in multiprocessor memory space).’
    
 
    “If it is correct, I would like to ask you following question, a) When defining 1 or 2 wait-state, how this wait-state value affect to RD and WR signal on the timing chart ?
    
 
    I think WR and RD change on CLKOUT's edge, therefore as far as CLKOUT cycle is NOT changed, WR and RD cycle(means duration time from signal rising to the next rising, or from rising to falling) will not be changed, I think, but is this correct ?”
    
 
    >> Kindly refer to page 475, of the Hardware Reference manual which explains the case for the wait state of 1.
    
 
    Please let me know in case you have any further queries related to this.
    
 
    Thanks,
    
 
    Harshit
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on Nov 22, 2014 1:48 PM
            
            
					
    
	
    

		
		
    
					
    Hello Harshit,
    
 
    Thank you very much for your reply, and sorry to take time to respond, since spending time to study HRM you instructed, and chapter of "Synchronous Mode Interface Timing".
    
 
    At first, I think I have to explain the original cause of the question was whether attached timing signal, /WR strobe when Synchronous Write, is correct or not, which is provided from our customer, driving under following setups.
    
 
    
 
    [External Memory Setup Register]
    
 
       EB0AM=10, EB0WS=010 
    
 
          (indicating,  Read : 2-waitstate,   Write : 1-waitstate)
    
 
    [Clocks]
    
 
       tCLKIN ： 40ns (CLKIN=25MHz)
    
 
       tCKOP ： 20ns (CLKOUT=50MHz, by using CLKDBL)
    
 
    The timing chart shows
    
 
    ≒60ns, from rising edge of /WR strobe to next rising edge.(It may be better to say falling edge since /WR is low active. )
    
 
    ≒40ns, the width of asserted /WR strobe.
    
 
    Subject to Figure 7-11 and related description of HRM page.475 you indicated, I think the attached timing chart is reasonable and explicable,
    
 
    but if you kindly confirmed it, it would be very much appreciated.
    
 
    Thank you again for your notes and subject to the provided information, ACK=High fixed and unchanged, thus I assume the system is using only one processor on the bus.
    
 
    You may doubt why ask these fundamentals for this legacy device.  In fact, this is old system but still work and like as many other cases, original engineer is not already there.
    
 
    Engineers who inherit to maintain the system has to check from scratch, so the sort of these questions often upwell, as same as the device which is newly released.
    
 
    These are background and if I receive additional questions, I will add here or create a new thread.
    
 
    Again, thank you very much for your helps, as always.
    
 
    Best Regards,
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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