When using Synchronous Read/Write as Bus Master, on ADSP-21161N, signal timing can be shown at Figure.19 on datasheet(Rev.C) page.31, as follows.
Here, it shows WR and RD signals are changed triggered by CLKIN.
On the other hand, when defining External Bank 0 Access Mode(EB0AM) as "10", Hardware Reference Table A-20 on page 938 is describing as follows.
Synchronous—processor RD and WR strobes change on CLKOUT’s edge—reads use the waitstate count setting from EBxWS (minimum EBxWS=001); writes are 1-wait state.
CLKOUT is output slightly delayed from CLKIN, as shown in Figure 11 of the datasheet page.23.
Thus, I believe we must consider Figure 11 and Figure 19 at the same time, for the timing of Synchronous Read/Write as Bus Mater.
Please correct me if I'm wrong.
If it is correct, I would like to ask you following question,
a) When defining 1 or 2 wait-state, how this wait-state value affect to RD and WR signal on the timing chart ?
I think WR and RD change on CLKOUT's edge, therefore as far as CLKOUT cycle is NOT changed, WR and RD cycle(means duration time from signal rising to the next rising, or from rising to falling) will not be changed, I think, but is this correct ?
If my thought is NOT correct, please let me know how the value of wait-state will affect to the timing chart.