Below is a table showing SHARC performance from Analog Devices website.
When I measured the number of cycles executing Talkthru_IIR_Accelerator example packaged in VDSP5.1, I got more cycles than cycles shown above. Total cycles measured is 31248. In the example, the number of biquads is 3 and data length is 512.
31248 / 512 = 60cycles. 60 / 3 biquads = 20 cycles. That is approximately 150ns. Much larger than described in tha table.
Could you explain why?
In the ADSP-21489 datasheet, the mentioned algorithm benchmarks are captured from the handwritten optimized assembly code (Core algorithm), but not for the Accelerator.
In most of these cases the core takes fewer cycles than the IIR accelerator. The difference between the cycles taken by the core and the accelerator is almost negligible for lower order IIR operations but becomes more significant for higher order IIR operations. This difference increases as the window size is increased.
Thanks & Regards
Can you please have a look into the library codes available in the VisualDSP++ installation directory, the path is given below.
...(VisualDSP++ installation directory)\214xx\lib\src\libdsp_src
Then could you share optimized IIR code in assembly with me if you have?
My application is time critical.
I measured cycles using iir library and I have got a result that shows 3~4 times cycles taken than described.
Biquad() packaged in DSP runtime library was used.
Target: ADSP-21489 ezlite kit
Total cycles measured: 10,310
The number of cycles/sample/biquad = 10,310 / 512 / 3 = 6.7 cycles
At 400MHz clock, it is 16.75ns (6.7 * 2.5ns). 3 times bigger.
I think that "Assumes two files in multichannel SIMD mode" would be an important condition.
Can you tell me in detail what the note underlined in red means?
You can find some of the ADSP-21364 application code examples in the below link.
ADSP-2136x Application Code Examples
It contains multichannel SIMD IIR code examples for ADSP-21364 processor that you can be modified to run on ADSP-21489 processor.