programming PCG for SPDIF clock

Hello,

I want to set internal adsp 21364 clock as a clock for sampling in SPDIF, using the SPDIF talkthru, I've programmed PCG correctly, but I recieve crackles with output audio signal. The code with comments is below.

#define CLKA_DIVIDER 8 //--provides SCLK serial clock to S/PDIF TX and SPORT0

#define FSA_DIVIDER 512//--provides Frame Sync to S/PDIF TX and SPORT0 (approx 48kHz)

#define CLKB_DIVIDER 2 //--provides HFCLK to S/PDIF TX

{

  *pPCG_CTLA_1 = CLKA_DIVIDER;

  *pPCG_CTLA_0 = FSA_DIVIDER | ENFSA | ENCLKA ;

  *pPCG_CTLB_1 = CLKB_DIVIDER | 0xC00000;

  *pPCG_CTLB_0 = ENCLKB ;

  *pPCG_PW = 0;

  *pPCG_SYNC = 0;

}

Sru :

void InitDAI(){

// Disable the pull-up resistors on all 20 pins

    *pDAI_PIN_PULLUP = 0x000FFFFF;

//  Tie the pin buffer input LOW.

    SRU(LOW,DAI_PB18_I);

//  Tie the pin buffer enable input LOW

    SRU(LOW,PBEN18_I);

    SRU(DAI_PB18_O,DIR_I);

    //  Clock in from SPDIF RX

    SRU(PCG_CLKA_O,SPORT0_CLK_I);//DIR_CLK_O

    //  Frame sync from SPDIF RX

    SRU(DIR_FS_O,SPORT0_FS_I);//DIR_FS_O //when i change this FS into PCG fs i recieve just crackles, but very loud

    //  Data in from SPDIF RX

    SRU(DIR_DAT_O,SPORT0_DA_I);

    // Clock on pin 7

    SRU(PCG_CLKA_O,DAI_PB07_I);//DIR_CLK_O

    SRU(HIGH,PBEN04_I);

    SRU(PCG_CLKB_O,DAI_PB04_I);//TUTAJ SPRAWDZAMY ZEGARY

    SRU(HIGH,PBEN17_I);

   

    // Frame sync on pin 8

    SRU(PCG_FSA_O,DAI_PB08_I);//DIR_FS_O

    // Data in on pin 5

    SRU(DAI_PB05_O , SPORT0_DB_I);

    // Tie the pin buffer enable inputs HIGH to drive DAI pins 7 and 8

    SRU(HIGH,PBEN07_I );

    SRU(HIGH,PBEN08_I );

//-----------------------------------------------------------------------------

//

//  Connect the DACs: The codec accepts a BCLK input from DAI pin 13 and

//          a LRCLK (a.k.a. frame sync) from DAI pin 14 and has four

//          serial data outputs to DAI pins 12, 11, 10 and 9

//

//          Connect DAC1 to SPORT1, using data output A

//          Connect DAC2 to SPORT1, using data output B

//          Connect DAC3 to SPORT2, using data output A

//          Connect DAC4 to SPORT2, using data output B

//

//          Connect MCLK from SPDIF to DAC on DAI Pin 6

//

//          Connect the clock and frame sync inputs to SPORT1 and SPORT2

//          should come from the SPDIF RX on DAI pins 7 and 8, respectively

//

//          Connect the SPDIF RX BCLK and LRCLK out to the DAC on DAI

//          pins 13 and 14, respectively.

//

//          All six DAC connections are always outputs from the SHARC

//          so tie the pin buffer enable inputs all high.

//

//------------------------------------------------------------------------

//  Connect the pin buffers to the SPORT data lines

    SRU(SPORT2_DB_O,DAI_PB09_I);

    SRU(SPORT2_DA_O,DAI_PB10_I);

    SRU(SPORT1_DB_O,DAI_PB11_I);

    SRU(SPORT1_DA_O,DAI_PB12_I);

//------------------------------------------------------------------------

//  Connect the clock, frame sync, and MCLK from the SPDIF RX directly

//    to the output pins driving the DACs.

    SRU(PCG_CLKA_O,DAI_PB13_I);//DIR_CLK_O

    SRU(PCG_FSA_O,DAI_PB14_I);//DIR_FS_O

    SRU(PCG_CLKB_O,DAI_PB06_I);//DIR_TDMCLK_O

//------------------------------------------------------------------------

//  Connect the SPORT clocks and frame syncs to the clock and

//    frame sync from the SPDIF receiver

    SRU(PCG_CLKA_O,SPORT1_CLK_I);//DIR_CLK_O

    SRU(PCG_CLKA_O,SPORT2_CLK_I);//DIR_CLK_O

    SRU(PCG_FSA_O,SPORT1_FS_I);//DIR_FS_O

    SRU(PCG_FSA_O,SPORT2_FS_I);//DIR_FS_O

//------------------------------------------------------------------------

//  Tie the pin buffer enable inputs HIGH to make DAI pins 6 & 9-14 outputs.

    SRU(HIGH,PBEN06_I);

    SRU(HIGH,PBEN09_I);

    SRU(HIGH,PBEN10_I);

    SRU(HIGH,PBEN11_I);

    SRU(HIGH,PBEN12_I);

    SRU(HIGH,PBEN13_I);

    SRU(HIGH,PBEN14_I);

}

can anybody tell what am i doing wrong? I just want to have SPDIF signal clocked by the internal clock, not the one recovered from SPDIF signal...

  • 0
    •  Analog Employees 
    on Mar 27, 2015 5:25 PM

    Hi,

    I understand from your problem description that you don’t want to use the generated SPDIF clock/FS etc.  Instead of that you are replacing it with the Clocks generated internally by the PCG.

    Can you explain the reason behind this?

    What is the ratio of the PCG clock w.r.t the one generated by SPDIF?

    You may want to make use of the SRC module where at the Input port, you can connect the SPDIF signals and at the output port you can connect the internally generated SPDIF signals.

    Kindly provide more details in order you support you better with the issue.

    Thanks,

    Harshit

  • 0
    •  Analog Employees 
    on Aug 2, 2018 2:56 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin