Post Go back to editing

intermittent booting please help

Can someone please help me Im really stuck

I built a ADSP-21261 custom board, the system seems to have successfully booted via from M2516 SPI flash (in master mode), however im finding a problem with intermittent booting,where the board doesn't successfully boot the system first time during power up, most of the time I have to power cycle the board quite a few times to get the board to boot correctly.

Note: the program is very simple it just toggles Flag1 so no PLL software setup was used and the clock config is set to 3:1, this is obviously used to test the the boot sequence.

I've read all most of the SHARCEE engineering docs referenced on the forum, so far I haven't found a solution or cause to why this is happening the docs does have alot of useful information which I have taken into consideration, but this problem seems unique.

This experiences seems similar to post https://ez.analog.com/message/138620#138620 however im using a ADSP-21261

Here is my setup

1) I'm using CCES 1.0.3

2) Here is my cldp command (which seems to work)

cldp -proc ADSP-21262 -emu "ICE-100" -driver "C:\Users\admin\CrossCore Embedded Studio\examples\21262_ezkit_lite_1.0.0\M25P16_Flasher\Debug\M2516_Flasher.dxe"   -cmd prog -erase all -format hex -file "C:\Users\admin\CrossCore Embedded Studio\examples\21262_ezkit_lite_1.0.0\Core_Timer\Debug\Core_Timer.ldr"  -cmd compare  -format hex  -offset 0  -file "C:\Users\admin\CrossCore Embedded Studio\examples\21262_ezkit_lite_1.0.0\Core_Timer\Debug\Core_Timer.ldr"

3) See attachment for my SHARC loader settings.

4) I'm using the default kernel, I'm using the following CrossCore Embedded Studio 1.0.3\SHARC\ldr\26x_spi.dxe

5) Find some attachments illustrating the problem

attachments.zip
Parents
  • Hi,

    PLL is the heart of the SHARC processors, and requires robust hardware and software handling.

    If you face problems based on PLL changes the following can be checked out in the system:

    1. Is the power-up specification met according to the data sheet (valid core and IO voltage, input clock, reset signal)?
    2. Are the CLK_CFG pins static (may change only during reset)?

    Can you also monitor CLOCK at the time of booting?

    The ADSP-2126x has separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement. The external supply must meet the 3.3 V requirement.

    Analog supply pin (AVDD) powers the ADSP-2126x’s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the AVDD pin. Can you make sure that the analog power filter circuit is same as mentioned in the datasheet on page 7.

    This should give us some idea.

    Please let us know if you have any further queries.

    Regards,

    Harshit

Reply
  • Hi,

    PLL is the heart of the SHARC processors, and requires robust hardware and software handling.

    If you face problems based on PLL changes the following can be checked out in the system:

    1. Is the power-up specification met according to the data sheet (valid core and IO voltage, input clock, reset signal)?
    2. Are the CLK_CFG pins static (may change only during reset)?

    Can you also monitor CLOCK at the time of booting?

    The ADSP-2126x has separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement. The external supply must meet the 3.3 V requirement.

    Analog supply pin (AVDD) powers the ADSP-2126x’s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the AVDD pin. Can you make sure that the analog power filter circuit is same as mentioned in the datasheet on page 7.

    This should give us some idea.

    Please let us know if you have any further queries.

    Regards,

    Harshit

Children
No Data