intermittent booting please help

Hi Klaus!, firstly thanks for the help, really appreciate it.

Power up timing: there is a minimum delay required between the FLASH Vcc going into regulation and S# going low.

see attachment here the flash section of my board, its a replica of the ez-kit flash section found in most of the board.

This seems unlikely to be a problem in your case unless your supply is really flaky.

There is also the power up timing of the processor itself, the requirements of which are described in the hardware reference manual.

I use a DP832 Rigol laboratory power supply,and my supply uses local low drop out regulators power up seems very normal in terms of ramp up time and noise measurements. see attachments.

signal integrity: make sure that the FLASH does not see ringing or non-monotonic edges on its clock line. Does the layout follow transmission line rules? Are your supplies stable and well decoupled

   I probed the clock line what I noticed is sometimes I don't always receive a stable clock, I have simple rules like keeping the clock line short and psu lines 1.2v and 3.3v decoupled seen on the diagram

When you zoom in on the first word, does the command always come out correct?

What does the reset line to the SHARC look like and how are you generating it? What about the clock?

Anything hanging off the JTAG pins?

 

It looks like on a few attempts the processor does not load the 256 32 it words. Since this is a hardwired functionality the part either gets reset again during the boot or hangs for some other reasons.

I found whilst responding there seems to be issues with the SPI clock no generating at all during boot OR sometimes the clock is just unstable all the time and explains why no stable read request commands are not showing

It looks it might be a clock stability issue, I will report back later my findings.. if anyone can throw a few tips I would appreciate it

Hi Klaus!, firstly thanks for the help, really appreciate it.

Power up timing: there is a minimum delay required between the FLASH Vcc going into regulation and S# going low.

see attachment here the flash section of my board, its a replica of the ez-kit flash section found in most of the board.

This seems unlikely to be a problem in your case unless your supply is really flaky.

There is also the power up timing of the processor itself, the requirements of which are described in the hardware reference manual.

I use a DP832 Rigol laboratory power supply,and my supply uses local low drop out regulators power up seems very normal in terms of ramp up time and noise measurements. see attachments.

signal integrity: make sure that the FLASH does not see ringing or non-monotonic edges on its clock line. Does the layout follow transmission line rules? Are your supplies stable and well decoupled

   I probed the clock line what I noticed is sometimes I don't always receive a stable clock, I have simple rules like keeping the clock line short and psu lines 1.2v and 3.3v decoupled seen on the diagram

When you zoom in on the first word, does the command always come out correct?

What does the reset line to the SHARC look like and how are you generating it? What about the clock?

Anything hanging off the JTAG pins?

 

It looks like on a few attempts the processor does not load the 256 32 it words. Since this is a hardwired functionality the part either gets reset again during the boot or hangs for some other reasons.

I found whilst responding there seems to be issues with the SPI clock no generating at all during boot OR sometimes the clock is just unstable all the time and explains why no stable read request commands are not showing

It looks it might be a clock stability issue, I will report back later my findings.. if anyone can throw a few tips I would appreciate it